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31. 发明申请

US20120276715A1 METHOD FOR MANUFACTURING COMBINED SUBSTRATE HAVING SILICON CARBIDE SUBSTRATE 审中-公开
标题翻译：用于制造具有碳化硅基底的组合衬底的方法
公开(公告)号：US20120276715A1
公开(公告)日：2012-11-01
申请号：US13395795
申请日：2011-06-17
申请人： Tsutomu Hori , Shin Harada , Makoto Sasaki , Hiroki Inoue , Kyoko Okita , Yasuo Namikawa , Satomi Itoh
发明人： Tsutomu Hori , Shin Harada , Makoto Sasaki , Hiroki Inoue , Kyoko Okita , Yasuo Namikawa , Satomi Itoh
IPC分类号： H01L21/762
CPC分类号： H01L29/7802 , H01L21/02002 , H01L21/02378 , H01L21/02529 , H01L21/0475 , H01L21/2007 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L2924/0002 , H01L2924/00
摘要： A connected substrate having a supporting portion and first and second silicon carbide substrates is prepared. The first silicon carbide substrate has a first backside surface connected to the supporting portion, a first front-side surface, and a first side surface connecting the first backside surface and the first front-side surface to each other. The second silicon carbide substrate has a second backside surface connected to the supporting portion, a second front-side surface, and a second side surface connecting the second backside surface and the second front-side surface to each other and forming a gap between the first side surface and the second side surface. A filling portion for filling the gap is formed. Then, the first and second front-side surfaces are polished. Then, the filling portion is removed. Then, a closing portion for closing the gap is formed.
摘要翻译：制备具有支撑部分和第一和第二碳化硅衬底的连接衬底。第一碳化硅衬底具有连接到支撑部分的第一背面，第一前侧表面和将第一背面和第一前侧表面相互连接的第一侧面。第二碳化硅衬底具有连接到支撑部分的第二背侧表面，第二前侧表面和将第二背面和第二前侧表面彼此连接并在第一前侧面之间形成间隙的第二侧表面侧表面和第二侧表面。形成用于填充间隙的填充部分。然后，对第一和第二前表面进行抛光。然后，将填充部分移除。然后，形成用于封闭间隙的封闭部分。

32. 发明授权

US08168515B2 Method for manufacturing semiconductor substrate 失效
标题翻译：半导体衬底的制造方法
公开(公告)号：US08168515B2
公开(公告)日：2012-05-01
申请号：US13062057
申请日：2010-04-27
申请人： Makoto Sasaki , Shin Harada , Taro Nishiguchi , Shinsuke Fujiwara , Yasuo Namikawa
发明人： Makoto Sasaki , Shin Harada , Taro Nishiguchi , Shinsuke Fujiwara , Yasuo Namikawa
IPC分类号： H01L21/20
CPC分类号： H01L29/7802 , C30B23/00 , C30B29/36 , C30B33/06 , H01L21/02378 , H01L21/02529 , H01L21/2007 , H01L29/045 , H01L29/0878 , H01L29/1608 , H01L29/66068 , H01L29/7395
摘要： A first silicon carbide substrate having a first back-side surface and a second silicon carbide substrate having a second back-side surface are prepared. The first and second silicon carbide substrates are placed so as to expose each of the first and second back-side surfaces in one direction. A connecting portion is formed to connect the first and second back-side surfaces to each other. The step of forming the connecting portion includes a step of forming a growth layer made of silicon carbide on each of the first and second back-side surfaces, using a sublimation method of supplying a sublimate thereto in the one direction.
摘要翻译：制备具有第一背面表面的第一碳化硅衬底和具有第二背面的第二碳化硅衬底。第一和第二碳化硅衬底被放置成在一个方向上暴露第一和第二后侧表面中的每一个。连接部形成为将第一和第二背面彼此连接。形成连接部分的步骤包括在第一和第二后侧表面中的每一个上形成由碳化硅制成的生长层的步骤，使用在一个方向上向其升华的升华方法。

33. 发明申请

US20120025208A1 METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND SILICON CARBIDE SUBSTRATE 审中-公开
标题翻译：制造碳化硅基体和碳化硅基体的方法
公开(公告)号：US20120025208A1
公开(公告)日：2012-02-02
申请号：US13258907
申请日：2010-09-29
申请人： Taro Nishiguchi , Takeyoshi Masuda , Makoto Sasaki , Shin Harada , Yasuo Namikawa , Shinsuke Fujiwara
发明人： Taro Nishiguchi , Takeyoshi Masuda , Makoto Sasaki , Shin Harada , Yasuo Namikawa , Shinsuke Fujiwara
IPC分类号： H01L29/161 , H01L21/762
CPC分类号： H01L29/7802 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/0475 , H01L21/187 , H01L29/045 , H01L29/1608 , H01L29/66068
摘要： A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; forming a Si film made of silicon on a main surface of the base substrate; fabricating a stacked substrate by placing the SiC substrate on and in contact with the Si film; and connecting the base substrate and the SiC substrate to each other by heating the stacked substrate to convert, into silicon carbide, at least a region making contact with the base substrate and a region making contact with the SiC substrate in the Si film.
摘要翻译：制造碳化硅基板的方法包括以下步骤：制备由碳化硅制成的基底基板和由单晶碳化硅制成的SiC基板; 在所述基底基板的主表面上形成由硅制成的Si膜; 通过将SiC衬底置于Si膜上并与其接触来制造堆叠衬底; 并且通过加热所述堆叠的基板将所述基底基板和所述SiC基板彼此连接，以将至少与所述基底基板接触的区域和与所述Si膜中的所述SiC基板接触的区域转化为碳化硅。

34. 外观设计

USD651992S1 Semiconductor substrate 有权
公开(公告)号：USD651992S1
公开(公告)日：2012-01-10
申请号：US29379485
申请日：2010-11-19
申请人： Taro Nishiguchi , Makoto Sasaki , Shin Harada , Shinsuke Fujiwara , Yasuo Namikawa
设计人： Taro Nishiguchi , Makoto Sasaki , Shin Harada , Shinsuke Fujiwara , Yasuo Namikawa

35. 发明申请

US20120273800A1 COMPOSITE SUBSTRATE HAVING SINGLE-CRYSTAL SILICON CARBIDE SUBSTRATE 审中-公开
标题翻译：具有单晶碳化硅基体的复合基板
公开(公告)号：US20120273800A1
公开(公告)日：2012-11-01
申请号：US13395494
申请日：2011-06-17
申请人： Tsutomu Hori , Shin Harada , Hiroki Inoue , Makoto Sasaki , Satomi Itoh , Yasuo Namikawa
发明人： Tsutomu Hori , Shin Harada , Hiroki Inoue , Makoto Sasaki , Satomi Itoh , Yasuo Namikawa
IPC分类号： H01L29/24
CPC分类号： H01L29/7802 , H01L21/02002 , H01L21/02529 , H01L21/02609 , H01L21/02667 , H01L29/045 , H01L29/1608 , H01L29/66068
摘要： A first vertex of a first single-crystal silicon carbide substrate and a second vertex of a second single-crystal silicon carbide substrate abut each other such that a first side of the first single-crystal silicon carbide substrate and a second side of the second single-crystal silicon carbide substrate are aligned. In addition, at least a part of the first side and at least a part of the second side abut on a third side of a third single-crystal silicon carbide substrate. Thus, in manufacturing a semiconductor device including a composite substrate, process fluctuations caused by a gap between the single-crystal silicon carbide substrates can be suppressed.
摘要翻译：第一单晶碳化硅衬底的第一顶点和第二单晶碳化硅衬底的第二顶点彼此邻接，使得第一单晶碳化硅衬底的第一侧和第二单晶碳化硅衬底的第二侧 - 晶体碳化硅衬底被对准。此外，第一侧的至少一部分和第二侧的至少一部分与第三单晶碳化硅基板的第三面邻接。因此，在制造包括复合衬底的半导体器件时，可以抑制由单晶碳化硅衬底之间的间隙引起的工艺波动。

36. 发明申请

US20120003811A1 METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：制造半导体基板的方法
公开(公告)号：US20120003811A1
公开(公告)日：2012-01-05
申请号：US13254947
申请日：2010-09-28
申请人： Makoto Sasaki , Shin Harada , Taro Noshiguchi , Kyoto Okita , Hideto Tamaso , Yasuo Namikawa
发明人： Makoto Sasaki , Shin Harada , Taro Noshiguchi , Kyoto Okita , Hideto Tamaso , Yasuo Namikawa
IPC分类号： H01L21/04
CPC分类号： H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/02612 , H01L21/02656 , H01L21/02667 , H01L21/047 , H01L29/66068
摘要： A first silicon carbide substrate has a first front-side surface and a first side surface. A second silicon carbide substrate has a second front-side surface and a second side surface. The second side surface is disposed such that a gap having an opening between the first and second front-side surfaces of the first and second silicon carbide substrates is disposed between the first side surface and the second side surface. A closing portion is provided to close the gap over the opening. By depositing sublimates from the first and second side surfaces onto the closing portion, a connecting portion is formed to connect the first and second side surfaces to each other so as to close the opening. After the step of forming the connecting portion, the closing portion is removed.
摘要翻译：第一碳化硅衬底具有第一前侧表面和第一侧表面。第二碳化硅衬底具有第二前侧表面和第二侧表面。第二侧表面设置成使得在第一和第二碳化硅衬底的第一和第二前侧表面之间具有开口的间隙设置在第一侧表面和第二侧表面之间。提供封闭部分以封闭开口上的间隙。通过将第一和第二侧表面的升华物沉积到封闭部分上，形成连接部分以将第一和第二侧表面彼此连接以便关闭开口。在形成连接部分的步骤之后，去除封闭部分。

37. 发明申请

US20100044721A1 METHOD OF PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：生产半导体器件和半导体器件的方法
公开(公告)号：US20100044721A1
公开(公告)日：2010-02-25
申请号：US12526731
申请日：2008-08-21
申请人： Kazuhiro Fujikawa , Shin Harada , Yasuo Namikawa , Takeyoshi Masuda
发明人： Kazuhiro Fujikawa , Shin Harada , Yasuo Namikawa , Takeyoshi Masuda
IPC分类号： H01L29/24 , H01L21/04
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/67109 , H01L29/45 , H01L29/66068 , Y10T117/1068 , Y10T117/1088
摘要： The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.
摘要翻译：本发明提供一种制造半导体器件的方法，该半导体器件能够通过在热处理步骤中充分抑制晶片的表面粗糙化以及其中性能恶化的半导体器件来抑制由于晶片的表面粗糙而导致的性能恶化造成表面粗糙度受到抑制。制造作为半导体器件的MOSFET的方法具有制备由碳化硅制成的晶片3的步骤和通过加热晶片3进行活化退火的活化退火步骤。在活化退火步骤中，晶片3被加热在包含由除了晶片3之外的发生源的SiC片61产生的碳化硅蒸气的气氛中。

38. 发明授权

US08643065B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08643065B2
公开(公告)日：2014-02-04
申请号：US12919992
申请日：2009-12-11
申请人： Kazuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
发明人： Kazuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
IPC分类号： H01L29/80
CPC分类号： H01L29/66068 , H01L21/0465 , H01L29/1066 , H01L29/1608 , H01L29/8083
摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.
摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。第一p型区域包括设置成包括上表面的基极区域和突出区域。基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。

39. 发明申请

US20110127585A1 LATERAL JUNCTION FIELD-EFFECT TRANSISTOR 审中-公开
标题翻译：横向连接场效应晶体管
公开(公告)号：US20110127585A1
公开(公告)日：2011-06-02
申请号：US13056071
申请日：2010-03-26
申请人： Kazuhiro Fujikawa , Shin Harada , Yasuo Namikawa
发明人： Kazuhiro Fujikawa , Shin Harada , Yasuo Namikawa
IPC分类号： H01L29/80
CPC分类号： H01L29/808 , H01L29/063 , H01L29/1066 , H01L29/1608 , H01L29/66068
摘要： A lateral junction field-effect transistor capable of preventing the occurrence of leakage current and realizing a sufficient withstand voltage can be provided. In a lateral JFET according to the present invention, a buffer layer is located on a main surface of a SiC substrate and includes a p-type impurity. A channel layer is located on the buffer layer and includes an n-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer. A source region and a drain region are of n-type and formed to be spaced from each other in a surface layer of the channel layer, and a p-type gate region is located in the surface layer of the channel layer and between the source region and the drain region. A barrier region is located in an interface region between the channel layer and the buffer layer and in a region located under the gate region and includes a p-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer.
摘要翻译：可以提供能够防止发生漏电流并实现足够的耐压的横向结型场效应晶体管。在根据本发明的横向JFET中，缓冲层位于SiC衬底的主表面上并且包括p型杂质。沟道层位于缓冲层上，并且包括具有比缓冲层中的p型杂质浓度高的浓度的n型杂质。源极区域和漏极区域是n型并且在沟道层的表面层中形成为彼此间隔开，并且p型栅极区域位于沟道层的表面层和源极区域和漏极区域。阻挡区域位于沟道层和缓冲层之间的界面区域中，并位于栅极区域下方的区域中，并且包括具有比缓冲层中的p型杂质浓度高的浓度的p型杂质。

40. 发明申请

US20110001144A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110001144A1
公开(公告)日：2011-01-06
申请号：US12919992
申请日：2009-12-11
申请人： Kuzuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
发明人： Kuzuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
IPC分类号： H01L31/0312 , H01L21/337
CPC分类号： H01L29/66068 , H01L21/0465 , H01L29/1066 , H01L29/1608 , H01L29/8083
摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.
摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。第一p型区域包括设置成包括上表面的基极区域和突出区域。基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。

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