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31. 发明授权

US4980747A Deep trench isolation with surface contact to substrate 失效
标题翻译：深沟槽隔离与表面接触衬底
公开(公告)号：US4980747A
公开(公告)日：1990-12-25
申请号：US259403
申请日：1988-10-18
申请人： Louis N. Hutter , James D. Goon , Shiu-Hang Yan , Gopal K. Rao
发明人： Louis N. Hutter , James D. Goon , Shiu-Hang Yan , Gopal K. Rao
IPC分类号： H01L21/74 , H01L21/763
CPC分类号： H01L21/763 , H01L21/743
摘要： A trench structure and fabrication technique is disclosed for isolating adjacent circuits in an integrated circuit. A trench (26) is coated with an oxidation barrier (18) of silicon to protect underlying semiconductor regions (34, 36) from crystal faults and dislocations caused by high temperature oxidation. The trench (26) includes a bottom (50) formed of the substrate (10). The trench (26) is filled with a conductive material which is in electrical contact with the substrate (10). A top surface contact electrode (74) is formed over the trench, in contact therewith, thereby also contacting the underlying substrate (10). For very narrow trenches, semiconductor areas (68, 70) are formed adjacent the top of the trench to thereby provide additional contact surface for the electrode (74).
摘要翻译：公开了用于隔离集成电路中的相邻电路的沟槽结构和制造技术。沟槽（26）涂覆有硅的氧化屏障（18），以保护底层半导体区域（34,36）免受由高温氧化引起的晶体故障和位错。沟槽（26）包括由衬底（10）形成的底部（50）。沟槽（26）填充有与衬底（10）电接触的导电材料。顶表面接触电极（74）形成在沟槽上方，与其接触，从而也接触下面的衬底（10）。对于非常窄的沟槽，半导体区域（68,70）形成在沟槽的顶部附近，从而为电极（74）提供额外的接触表面。

32. 发明授权

US4819052A Merged bipolar/CMOS technology using electrically active trench 失效
标题翻译：合并双极/ CMOS技术使用电活动沟槽
公开(公告)号：US4819052A
公开(公告)日：1989-04-04
申请号：US945796
申请日：1986-12-22
申请人： Louis N. Hutter
发明人： Louis N. Hutter
IPC分类号： H01L21/76 , H01L21/74 , H01L21/822 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L29/78
CPC分类号： H01L21/8249 , H01L21/743 , H01L27/0623
摘要： Disclosed is a structure and method of fabricating bipolar and MOSFET devices isolated by an electrically active trench. A doped epitaxial layer (24) is formed on semiconductor substrate (10). A trench (36) is formed through the epitaxial layer (24) down to the substrate (10). The trench (36) is filled with a conductive material (54) and a topside contact (182) is formed in electrical contact with the conductive trench. A bipolar transistor (176) is formed in the epitaxial area (38) on one side of the trench (36) and a MOSFET transistor (178) is formed in the epitaxial area (40) on the other side of the trench (36). Plural contacts (200-206) can be made to the top surface of the trench (186), thereby maintaining the underlying substrate (10) at a desired and uniform potential.

33. 发明授权

US06737326B2 Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect 有权
标题翻译：在多层金属钨插头互连中集成薄膜电阻的方法
公开(公告)号：US06737326B2
公开(公告)日：2004-05-18
申请号：US09852921
申请日：2001-05-10
申请人： Philipp Steinmann , Stuart M. Jacobsen , Louis N. Hutter , Fred D. Bailey
发明人： Philipp Steinmann , Stuart M. Jacobsen , Louis N. Hutter , Fred D. Bailey
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L21/32051 , H01L23/522 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via (42) etch and fill, the thin film resistor material (62) is deposited. The metal interconnect layer (76) is then deposited, including any barrier layers desired. The metal leads (70) are then etched together with the shape of the thin film resistor (60). The metal (76) over the thin film resistor (60) is then removed.
摘要翻译：一种用于将薄膜电阻器集成到互连工艺流程中的方法，其中一个金属层用作硬掩模。在通孔（42）蚀刻和填充之后，沉积薄膜电阻器材料（62）。然后沉积金属互连层（76），包括所需的任何阻挡层。然后将金属引线（70）与薄膜电阻器（60）的形状一起蚀刻。然后去除薄膜电阻器（60）上方的金属（76）。

34. 发明授权

US06683380B2 Integrated circuit with bonding layer over active circuitry 有权
标题翻译：在有源电路上具有接合层的集成电路
公开(公告)号：US06683380B2
公开(公告)日：2004-01-27
申请号：US10191453
申请日：2002-07-10
申请人： Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
发明人： Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
IPC分类号： H01L2348
CPC分类号： H01L24/49 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05552 , H01L2224/05554 , H01L2224/05644 , H01L2224/05664 , H01L2224/0603 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/4847 , H01L2224/48644 , H01L2224/48664 , H01L2224/48764 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49175 , H01L2224/49431 , H01L2224/4945 , H01L2224/85191 , H01L2924/0001 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48744
摘要： An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.
摘要翻译：一种具有直接在其有源电路上的接合表面（12）的集成电路器件（10），以及制造这种集成电路的方法（图2A-2E）。为了形成接合表面（12），晶片（20）在其金属化层（21）上设有通孔（24），然后涂覆有种子金属层（25）。电镀图案（26）形成在晶片（20）上，暴露种子金属层（25）的部分并阻挡种子金属层（25）的其余部分。这些暴露部分镀有连续的金属层（27,28,29），由此形成具有填充通孔（24）的多个层叠堆叠（200）的接合表面（12）。然后除去种子金属层（25）的电镀图案和非电镀部分。

35. 发明授权

US06534364B1 Tunnel diode layout for an EEPROM cell for protecting the tunnel diode region 失效
标题翻译：用于保护隧道二极管区域的EEPROM单元的隧道二极管布局
公开(公告)号：US06534364B1
公开(公告)日：2003-03-18
申请号：US08949826
申请日：1997-10-14
申请人： John P. Erdeljac , Louis N. Hutter
发明人： John P. Erdeljac , Louis N. Hutter
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7883 , Y10S438/981
摘要： A tunnel diode construction 12 for an EEPROM device 10, and method for making it are shown. A tank 13 is provided at a surface of a semiconductor substrate 5 containing a doped diffused tunnel region 46. A layer of insulation 38 is provided over the surface of the substrate with a first thickness 48 to provide a tunnel oxide over at least part of the tunnel region and a second, larger, thickness 39 elsewhere. A conducting floating gate 19 is provided above the doped diffused tunnel region 46 and at least part of the tank 13, on the layer of insulation 38. The floating gate 19 extends over the oxide 38 beyond the lateral boundaries of the doped diffused tunnel region 46 in every direction to terminate over the second thickness of oxide 39 over the tank 13. To complete the EEPROM device 10, an MOS transistor 15 having source 21 and drain 27 doped regions provided in the substrate 5, with a portion 29 of the floating gate 19 capacitively coupled to a control gate 25 and extending over at least part of a channel region 28 of the MOS device.
摘要翻译：示出了用于EEPROM装置10的隧道二极管结构12及其制造方法。在包含掺杂扩散隧道区域46的半导体衬底5的表面处设置有罐13。在衬底的表面上设置有绝缘层38，其具有第一厚度48，以在第一厚度48的至少一部分上提供隧道氧化物隧道区域，另一个较大的厚度39。在绝缘层38上方的掺杂扩散隧道区域46和槽13的至少一部分上方设有导电浮置栅极19.浮动栅极19延伸超过掺杂扩散隧道区域46的横向边界在每个方向上终止在罐13上的第二厚度的氧化物39上。为了完成EEPROM器件10，具有设置在衬底5中的源极21和漏极27掺杂区域的MOS晶体管15与浮动栅极电容耦合到控制栅极25并在MOS器件的沟道区域28的至少一部分上延伸。

36. 发明授权

US5719421A DMOS transistor with low on-resistance and method of fabrication 失效
标题翻译：具有低导通电阻和制造方法的DMOS晶体管
公开(公告)号：US5719421A
公开(公告)日：1998-02-17
申请号：US775758
申请日：1996-12-31
申请人： Louis N. Hutter , John P. Erdeljac
发明人： Louis N. Hutter , John P. Erdeljac
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/0692 , H01L29/0696 , H01L29/1095 , H01L29/66659 , H01L29/66689 , H01L29/7835 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/1045 , H01L29/42368
摘要： A DMOS transistor (50) includes an Nwell (70); a Dwell (76) formed in the Nwell (70); a source region (78) formed in the Dwell (78), a channel region (80) defined between an edge of the source region (78) and an edge of the Nwell (70); a gate (86) extending over the channel region (80); and a p+ backgate contact region (90) formed in the source region (78) so as to counterdope and extend through a first portion of the source region (78) to contact the Dwell (76). The formation of the p+ backgate contact region through the source region (78) eliminates the need for a large annular shaped source region resulting in a considerable reduction in both device area and on-resistance.
摘要翻译： DMOS晶体管（50）包括N阱（70）; 形成在Nwell（70）中的停留（76）; 形成在停留孔（78）中的源极区（78），限定在源区（78）的边缘与Nwell（70）的边缘之间的沟道区（80）在所述通道区域（80）上延伸的门（86）; 以及形成在源极区域（78）中的p +后盖接触区域（90），以便反射并延伸穿过源极区域（78）的第一部分以接触停留区域（76）。通过源极区域（78）形成p +背栅接触区域消除了对大的环形源极区域的需要，导致器件面积和导通电阻的显着降低。

37. 发明授权

US5455447A Vertical PNP transistor in merged bipolar/CMOS technology 失效
标题翻译：并联双极/ CMOS技术中的垂直PNP晶体管
公开(公告)号：US5455447A
公开(公告)日：1995-10-03
申请号：US954605
申请日：1992-09-30
申请人： Louis N. Hutter , Joe R. Trogolo
发明人： Louis N. Hutter , Joe R. Trogolo
IPC分类号： H01L27/06 , H01L29/732 , H01L29/72 , H01L27/10 , H01L27/15
CPC分类号： H01L29/7322 , H01L27/0623
摘要： A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer (52d) and into a base region (54c). The base region (54c) is formed in the same processing step as the N well region (54b) of the PMOS transistor (42) and the collection region (54a) of the NPN transistor (40). By diffusing into the base region (54c), the width between the collector (84) and emitter (64e) is reduced. The emitter (64e) can be formed in conjunction with the source and drain regions of the PMOS transistor (42). The vertical PNP transistor (46) is laterally isolated from the other transistor devices by an annular ring formed from an N+ region (50c) formed in conjunction with an N+ DUF region (50a) used in the NPN transistor (40), and a N+ region (56b) formed in conjunction with an N+ collector region (56a) of the NPN transistor (40). An N+ DUF region (50b) may also be used in connection with the PMOS transistor (42).
摘要翻译：用于合并双极/ CMOS技术的垂直PNP结构具有作为集电极区的P +掩埋层（84），其通过N-掩埋层（82）与P衬底（48）隔离。 P +掩埋层（84）向下扩散到N埋层（82）中并向上扩散到P-外延层（52d）中并进入基极区（54c）。基极区域（54c）以与PMOS晶体管（42）的N阱区域（54b）和NPN晶体管（40）的收集区域（54a）相同的处理步骤形成。通过扩散到基极区域（54c）中，收集器（84）和发射极（64e）之间的宽度减小。发射极（64e）可以与PMOS晶体管（42）的源极和漏极区域结合形成。垂直PNP晶体管（46）通过由与NPN晶体管（40）中使用的N + DUF区域（50a）形成的N +区域（50c）形成的环形环与其它晶体管器件横向隔离，并且N + 区域（56b）与NPN晶体管（40）的N +集电极区（56a）结合形成。 N + DUF区（50b）也可以与PMOS晶体管（42）结合使用。

38. 发明授权

US5057443A Method for fabricating a trench bipolar transistor 失效
标题翻译：制造沟槽双极晶体管的方法
公开(公告)号：US5057443A
公开(公告)日：1991-10-15
申请号：US523436
申请日：1990-05-14
申请人： Louis N. Hutter
发明人： Louis N. Hutter
IPC分类号： H01L21/74 , H01L21/762 , H01L29/08 , H01L29/732
CPC分类号： H01L29/732 , H01L21/743 , H01L21/76294 , H01L29/0821
摘要： A bipolar transistor formed in a trench depression such that a single impurity diffusing step is effective to form a buried collector layer electrically connected to a vertical collector conductor. The lateral diffusion forming the vertical collector conductor is effective to form the conductor with a uniform vertical doping profile, thereby reducing non-uniform series collector resistance characteristics. A trench depression sidewall dielectric is formed, and the trench is filled with a transistor silicon material by a selective epitaxial process. Base and emitter region are then formed in the collector epitaxial material.
摘要翻译：形成在沟槽凹陷中的双极晶体管，使得单个杂质扩散步骤有效地形成电连接到垂直集电极导体的掩埋集电极层。形成垂直集电极导体的横向扩散有效地形成具有均匀垂直掺杂分布的导体，从而减少不均匀的集电极电阻特性。形成沟槽凹陷侧壁电介质，并且通过选择性外延工艺用沟槽填充晶体管硅材料。然后在集电极外延材料中形成基极和发射极区域。

39. 发明授权

US4929996A Trench bipolar transistor 失效
标题翻译：沟槽双极晶体管
公开(公告)号：US4929996A
公开(公告)日：1990-05-29
申请号：US213212
申请日：1988-06-29
申请人： Louis N. Hutter
发明人： Louis N. Hutter
IPC分类号： H01L21/74 , H01L21/762 , H01L29/08 , H01L29/732
CPC分类号： H01L29/0821 , H01L21/743 , H01L21/76294 , H01L29/732
摘要： A bipolar transistor formed in a trench depression such that a single impurity diffusing step is effective to form a buried collector layer electrically connected to a vertical collector conductor. The lateral diffusion forming the vertical collector conductor is effective to form the conductor with a uniform vertical doping profile, thereby reducing non-uniform series collector resistance characteristics. A trench depression sidewall dielectric is formed, and the trench is filled with a transistor silicon material by a selective epitaxial process. Base and emitter region are then formed in the collector epitaxial material.
摘要翻译：形成在沟槽凹陷中的双极晶体管，使得单个杂质扩散步骤有效地形成电连接到垂直集电极导体的掩埋集电极层。形成垂直集电极导体的横向扩散有效地形成具有均匀垂直掺杂分布的导体，从而减少不均匀的集电极电阻特性。形成沟槽凹陷侧壁电介质，并且通过选择性外延工艺用沟槽填充晶体管硅材料。然后在集电极外延材料中形成基极和发射极区域。

40. 发明授权

US4855244A Method of making vertical PNP transistor in merged bipolar/CMOS technology 失效
标题翻译：在合并双极/ CMOS技术中制造垂直PNP晶体管的方法
公开(公告)号：US4855244A
公开(公告)日：1989-08-08
申请号：US69358
申请日：1987-07-02
申请人： Louis N. Hutter , Joe R. Trogolo
发明人： Louis N. Hutter , Joe R. Trogolo
IPC分类号： H01L21/761 , H01L21/8228 , H01L21/8249 , H01L27/06
CPC分类号： H01L21/761 , H01L21/82285 , H01L21/8249 , H01L27/0623
摘要： A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer (52d) and into a base region (54c). The base region (54c) is formed in the same processing step as the N well region (54b) of the PMOS transistor (42) and the collection region (54a) of the NPN transistor (40). By diffusing into the base region (54c), the width between the collector (84) and emitter (64e) is reduced. The emitter (64e) can be formed in conjunction with the source and drain regions of the PMOS transistor (42). The vertical PNP transistor (46) is laterally isolated from the other transistor devices by an annular ring formed from an N+ region (50c) formed in conjunction with an N+ DUF region (50a) used in the NPN transistor (40), and a N+ region (56b) formed in conjunction with an N+ collector region (56a) of the NPN transistor (40). An N+ DUF region (50b) may also be used in conjunction with the PMOS transistor (42).
摘要翻译：用于合并双极/ CMOS技术的垂直PNP结构具有作为集电极区的P +掩埋层（84），其通过N-掩埋层（82）与P衬底（48）隔离。 P +掩埋层（84）向下扩散到N埋层（82）中并向上扩散到P-外延层（52d）中并进入基极区（54c）。基极区域（54c）以与PMOS晶体管（42）的N阱区域（54b）和NPN晶体管（40）的收集区域（54a）相同的处理步骤形成。通过扩散到基极区域（54c）中，收集器（84）和发射极（64e）之间的宽度减小。发射极（64e）可以与PMOS晶体管（42）的源极和漏极区域结合形成。垂直PNP晶体管（46）通过由与NPN晶体管（40）中使用的N + DUF区域（50a）形成的N +区域（50c）形成的环形环与其它晶体管器件横向隔离，并且N + 区域（56b）与NPN晶体管（40）的N +集电极区（56a）结合形成。 N + DUF区域（50b）也可以与PMOS晶体管（42）结合使用。

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