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1. 发明授权

US06737326B2 Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect 有权
标题翻译：在多层金属钨插头互连中集成薄膜电阻的方法
公开(公告)号：US06737326B2
公开(公告)日：2004-05-18
申请号：US09852921
申请日：2001-05-10
申请人： Philipp Steinmann , Stuart M. Jacobsen , Louis N. Hutter , Fred D. Bailey
发明人： Philipp Steinmann , Stuart M. Jacobsen , Louis N. Hutter , Fred D. Bailey
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L21/32051 , H01L23/522 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via (42) etch and fill, the thin film resistor material (62) is deposited. The metal interconnect layer (76) is then deposited, including any barrier layers desired. The metal leads (70) are then etched together with the shape of the thin film resistor (60). The metal (76) over the thin film resistor (60) is then removed.
摘要翻译：一种用于将薄膜电阻器集成到互连工艺流程中的方法，其中一个金属层用作硬掩模。在通孔（42）蚀刻和填充之后，沉积薄膜电阻器材料（62）。然后沉积金属互连层（76），包括所需的任何阻挡层。然后将金属引线（70）与薄膜电阻器（60）的形状一起蚀刻。然后去除薄膜电阻器（60）上方的金属（76）。

2. 发明授权

US6025231A Self aligned DMOS transistor and method of fabrication 失效
标题翻译：自对准DMOS晶体管及其制造方法
公开(公告)号：US6025231A
公开(公告)日：2000-02-15
申请号：US25678
申请日：1998-02-18
申请人： Louis N. Hutter , John P. Erdeljac , James R. Todd
发明人： Louis N. Hutter , John P. Erdeljac , James R. Todd
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/7835 , H01L29/0615 , H01L29/1083 , H01L29/42368
摘要： A method for fabricating a self-aligned DMOS transistor is provided. The method includes forming a passivation layer (18, 68) on an oxide layer (16, 66) of a substrate (12, 56). The oxide layer (16, 66) is then removed from the surface of the substrate (12, 56) where it is exposed through the passivation layer (18, 68). A reduced surface field region (36, 74) is then formed where the surface of the substrate (12, 56) is exposed through the passivation layer (18, 68). An oxide layer (38, 80) is then formed on the reduced surface field region (36, 74).
摘要翻译：提供一种制造自对准DMOS晶体管的方法。该方法包括在衬底（12,56）的氧化物层（16,66）上形成钝化层（18,68）。然后从衬底（12,56）的表面去除氧化物层（16,66），在衬底的表面上暴露于钝化层（18,68）。然后形成还原表面场区（36,74），其中衬底（12,56）的表面通过钝化层（18,68）暴露。然后在还原表面场区域（36,74）上形成氧化物层（38,80）。

3. 发明授权

US5554873A Semiconductor device having polysilicon resistor with low temperature coefficient 失效
标题翻译：具有低温系数的多晶硅电阻器的半导体装置
公开(公告)号：US5554873A
公开(公告)日：1996-09-10
申请号：US475116
申请日：1995-06-07
申请人： John P. Erdeljac , Louis N. Hutter
发明人： John P. Erdeljac , Louis N. Hutter
IPC分类号： H01L21/02 , H01L21/3215 , H01L27/06 , H01L27/02
CPC分类号： H01L28/20 , H01L21/32155 , H01L27/0688 , Y10S148/136 , Y10S148/146 , Y10S257/904 , Y10S438/934
摘要： A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).
摘要翻译：具有中等薄层电阻和低电阻温度系数的p型多晶硅电阻器（56）的半导体器件通过双级多晶硅工艺形成。该工艺还产生n沟道晶体管和p沟道晶体管（44,50），具有上和下n型多晶硅电容器板（36,26）的电容器，具有高薄层电阻的n型多晶硅电阻器（32）和n 型电阻器（34）。用于形成p沟道晶体管（50）的源极/漏极区域（48）的p型掺杂反向型n型第二级多晶硅以形成p型多晶硅电阻器（56）而不影响电容器板（36,26）或n 型电阻器（32,34）。

4. 发明授权

US5436179A Semiconductor process for manufacturing semiconductor devices with increased operating voltages 失效
标题翻译：用于制造具有增加的工作电压的半导体器件的半导体工艺
公开(公告)号：US5436179A
公开(公告)日：1995-07-25
申请号：US177888
申请日：1994-01-05
申请人： John P. Erdeljac , Louis N. Hutter
发明人： John P. Erdeljac , Louis N. Hutter
IPC分类号： H01L27/06 , H01L21/331
CPC分类号： H01L27/0623 , Y10S148/01
摘要： A bipolar transistor is formed on a substrate of a first (P) conductivity type by: forming a collector region (20) of the second conductivity type (N) in the substrate; forming an adjust region (27) of the first (P) conductivity type in the collector region (20); forming a base region (36) of the first (P) conductivity type in the collector region (20), the base region (36) containing the adjust region (27); and forming an emitter region (11) of the second (N) conductivity type in the adjust region (27). The base region (36) is deeper than and more heavily doped than the adjust region (27). The adjust region (27) alters the doping profile of the base-collector junction on the collector (20) side of the junction to increase the breakdown voltage of the transistor.
摘要翻译：通过在衬底中形成第二导电类型（N）的集电极区域（20），在第一（P）导电类型的衬底上形成双极晶体管; 在所述集电区域（20）中形成所述第一（P）导电类型的调节区域（27）。在所述集电区域（20）中形成所述第一（P）导电类型的基极区域（36），所述基极区域（36）包含所述调整区域（27）; 以及在所述调节区域（27）中形成所述第二（N）导电类型的发射极区域（11）。基极区域（36）比调整区域（27）更深，并且掺杂得更多。调整区域（27）改变了结的集电极（20）侧的基极 - 集电极结的掺杂分布，以增加晶体管的击穿电压。

5. 发明授权

US5171699A Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication 失效
标题翻译：内置基于N阱CMOS的BiCMOS工艺和制造方法的垂直DMOS晶体管结构
公开(公告)号：US5171699A
公开(公告)日：1992-12-15
申请号：US592108
申请日：1990-10-03
申请人： Louis N. Hutter , John P. Erdeljac
发明人： Louis N. Hutter , John P. Erdeljac
IPC分类号： H01L21/336 , H01L21/761 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L29/78
CPC分类号： H01L29/66719 , H01L21/761 , H01L21/8238 , H01L21/8249 , H01L29/66712 , H01L29/7809 , H01L27/088
摘要： An integrated circuit is provided wherein bipolar, CMOS and DMOS devices are merged together on one chip with fabrication taking place from a CMOS point of view rather than from a bipolar point of view as in the prior art and p-type epitaxial silicon is used as opposed to n-type epitaxial silicon in the prior art. The integrated circuit uses a P+ substrate upon which a P-epitaxial layer is formed. N+ buried regions isolate the DMOS, PMOS and NPN bipolar devices from the P-epitaxial layer. Each of the devices is formed in a N-well with a first level of polysilicon gate layer providing both the gate and masking for the backgate diffusion of the DMOS device and a sidewall oxide later formed on the first level gate layer to control the diffusion of the source and drain regions of the DMOS device to control channel length. A second level of polysilicon layer provides the gate structures for the CMOS devices as well as one plate of a capacitor. The second level of polysilicon acts as a mask for the source and drain region implants of the CMOS devices. A sidewall oxide later formed on the second polysilicon level further controls the channel lengths of the CMOS structures. A third level of polysilicon provides the second capacitor plate for the capacitor. The DMOS device is isolated from the remaining circuitry by the p-type epitaxial layer and the peripheral portion of the DMOS device is terminated by a PN junction.
摘要翻译：提供了一种集成电路，其中双极性，CMOS和DMOS器件在一个芯片上合并在一起，其制造从CMOS观点而不是从现有技术的双极观点出发，并且p型外延硅被用作与现有技术中的n型外延硅相反。集成电路使用其上形成有P外延层的P +衬底。 N +掩埋区域从P-外延层隔离DMOS，PMOS和NPN双极器件。每个器件形成在具有第一级多晶硅栅极层的N阱中，其提供用于DMOS器件的背栅扩散的栅极和掩模，以及稍后形成在第一级栅极层上的侧壁氧化物以控制扩散 DMOS器件的源极和漏极区域来控制沟道长度。第二级多晶硅层提供CMOS器件的栅极结构以及电容器的一个板。第二级多晶硅作为CMOS器件的源极和漏极区域掩模的掩模。稍后形成在第二多晶硅层上的侧壁氧化物进一步控制CMOS结构的沟道长度。第三级多晶硅为电容器提供第二电容器板。 DMOS器件通过p型外延层与剩余电路隔离，并且DMOS器件的外围部分由PN结终止。

6. 发明授权

US4926233A Merged trench bipolar-CMOS transistor fabrication process 失效
标题翻译：合并沟槽双极CMOS晶体管制造工艺
公开(公告)号：US4926233A
公开(公告)日：1990-05-15
申请号：US213006
申请日：1988-06-29
申请人： Louis N. Hutter
发明人： Louis N. Hutter
IPC分类号： H01L21/8249 , H01L27/06
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A BICMOS fabrication technique utilizing trench depressions for forming bipolar and PMOS transistors. The trench depressions each have high conductivity diffusion sidewalls for functioning respectively as a collector conductor and a guard ring. The trench depressions include thin dielectric sidewalls for allowing small area transistors. NMOS devices are formed within the substrate material. The fabrication process allows a high degree of self-alignment and thus reduces numerous masking steps.
摘要翻译：利用沟槽凹陷形成双极和PMOS晶体管的BICMOS制造技术。沟槽凹陷各自具有高导电性扩散侧壁，用于分别用作集电极导体和保护环。沟槽凹陷包括用于允许小面积晶体管的薄电介质侧壁。 NMOS器件形成在衬底材料内。制造工艺允许高程度的自对准，从而减少许多掩蔽步骤。

7. 发明授权

US06979615B2 System and method for forming a semiconductor with an analog capacitor using fewer structure steps 有权
公开(公告)号：US06979615B2
公开(公告)日：2005-12-27
申请号：US10243405
申请日：2002-09-12
申请人： Imran M. Khan , Louis N. Hutter , James Todd , Jozef C. Mitros , William E. Nehrer
发明人： Imran M. Khan , Louis N. Hutter , James Todd , Jozef C. Mitros , William E. Nehrer
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8242
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

8. 发明授权

US06706635B2 Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis 有权
标题翻译：建立低电压系数和滞后的高精度模拟电容的创新方法
公开(公告)号：US06706635B2
公开(公告)日：2004-03-16
申请号：US10163450
申请日：2002-06-05
申请人： Imran M. Khan , William E. Nehrer , James Todd , Weidong Tian , Louis N. Hutter
发明人： Imran M. Khan , William E. Nehrer , James Todd , Weidong Tian , Louis N. Hutter
IPC分类号： H01L21302
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/76838 , H01L27/0805
摘要： The present invention relates to a method for forming an anlog capacitor on a semiconductor substrate. The method comprises forming a field oxide over a portion of the substrate, and forming a polysilicon layer over the field oxide layer, and subsequently forming a silicide over the polysilicon layer. A first interlayer dielectric layer is formed over the substrate, and a capacitor masking pattern is formed. The first interlayer dielectric is etched using the capacitor masking pattern as a mask and the silicide layer as an etch stop, and a thin dielectric is formed over the substrate. A contact masking pattern is formed over the substrate, and a subsequent etch is performed on the thin dielectric and the first interlayer dielectric using the silicide and substrate as an etch stop. A metal layer is deposited over the substrate, and is subsequently planarized, thereby defining an analog capacitor.
摘要翻译：本发明涉及一种在半导体衬底上形成anlog电容器的方法。该方法包括在衬底的一部分上形成场氧化物，并在场氧化物层上形成多晶硅层，随后在多晶硅层上形成硅化物。在衬底上形成第一层间电介质层，形成电容器屏蔽图案。使用电容器掩模图案作为掩模蚀刻第一层间电介质，并且将硅化物层作为蚀刻停止层，并在衬底上形成薄的电介质。在衬底上形成接触掩模图案，并且使用硅化物和衬底作为蚀刻停止层，在薄电介质和第一层间电介质上进行随后的蚀刻。金属层沉积在衬底上，随后被平坦化，从而限定模拟电容器。

9. 发明授权

US06432791B1 Integrated circuit capacitor and method 有权
标题翻译：集成电路电容及方法
公开(公告)号：US06432791B1
公开(公告)日：2002-08-13
申请号：US09548061
申请日：2000-04-12
申请人： Louis N. Hutter , Peter S. Ying , Imran Khan
发明人： Louis N. Hutter , Peter S. Ying , Imran Khan
IPC分类号： H01L218242
CPC分类号： H01L27/0629
摘要： Capacitors for integrated circuits with a common polysilicon layer for both MOS gates (274, 276, 278) and capacitor (270) lower plates but with implanted doping for the gates and masked diffusive doping for the capacitor plates.
摘要翻译：用于集成电路的电容器具有用于两个MOS栅极（274,276,278）和电容器（270）的公共多晶硅层，但具有用于栅极的注入掺杂和用于电容器板的掩蔽扩散掺杂。

10. 发明授权

US06424005B1 LDMOS power device with oversized dwell 有权
标题翻译： LDMOS功率器件具有超大的驻留
公开(公告)号：US06424005B1
公开(公告)日：2002-07-23
申请号：US09205657
申请日：1998-12-03
申请人： Chin-Yu Tsai , Taylor R. Efland , Sameer Pendharkar , John P. Erdeljac , Jozef Mitros , Jeffrey P. Smith , Louis N. Hutter
发明人： Chin-Yu Tsai , Taylor R. Efland , Sameer Pendharkar , John P. Erdeljac , Jozef Mitros , Jeffrey P. Smith , Louis N. Hutter
IPC分类号： H01L31113
CPC分类号： H01L29/66689 , H01L29/086 , H01L29/0878 , H01L29/42368 , H01L29/7816
摘要： An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region (18), which permits the n-type region of the Dwell to diffuse under the gate region (18) an sufficient distance to eliminate misalignment effects.
摘要翻译： LDMOS器件（10,20,50,60）采用最小的特征尺寸制造方法制造，但克服了不对准Dwells的潜在问题（13）。驻留（13）略微夸大，使得其n型掺杂剂被注入超过栅极区域（18）的源极边缘，这允许Dwell的n型区域在栅极区域（18）下扩散到足够的距离消除不对准效应。

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