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31. 发明申请

US20120153482A1 STRUCTURE AND METHODS OF FORMING CONTACT STRUCTURES 有权
标题翻译：形成接触结构的结构和方法
公开(公告)号：US20120153482A1
公开(公告)日：2012-06-21
申请号：US13405443
申请日：2012-02-27
申请人： Ying Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Ying Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/485 , H01L21/28
CPC分类号： H01L21/76844 , H01L21/76846 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A contact structure and a method of forming the contact structure. The structure includes: a silicide layer on and in direct physical contact with a top substrate surface of a substrate; an electrically insulating layer on the substrate; and an aluminum plug within the insulating layer. The aluminum plug has a thickness not exceeding 25 nanometers in a direction perpendicular to the top substrate surface. The aluminum plug extends from a top surface of the silicide layer to a top surface of the insulating layer. The aluminum plug is in direct physical contact with the top surface of the silicide layer and is in direct physical contact with the silicide layer. The method includes: forming the silicide layer on and in direct physical contact with the top substrate surface of the substrate; forming the electrically insulating layer on the substrate; and forming the aluminum plug within the insulating layer.
摘要翻译：接触结构和形成接触结构的方法。该结构包括：与衬底的顶部衬底表面直接物理接触的硅化物层; 基板上的电绝缘层; 和绝缘层内的铝塞。该铝塞的垂直于顶部基板表面的方向的厚度不超过25纳米。铝塞从硅化物层的顶表面延伸到绝缘层的顶表面。铝插塞与硅化物层的顶表面直接物理接触并与硅化物层直接物理接触。该方法包括：在衬底的顶部衬底表面上直接物理接触硅化物层; 在基板上形成电绝缘层; 以及在所述绝缘层内形成所述铝塞。

32. 发明授权

US08133810B2 Structure for metal cap applications 有权
标题翻译：金属盖应用结构
公开(公告)号：US08133810B2
公开(公告)日：2012-03-13
申请号：US12881806
申请日：2010-09-14
申请人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/76885 , H01L21/76826 , H01L21/76834 , H01L21/7684 , H01L21/76849
摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.
摘要翻译：提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

33. 发明申请

US20100001253A1 Method for delineation of phase change memory cell via film resistivity modification 有权
标题翻译：通过膜电阻率修饰来描绘相变记忆单元的方法
公开(公告)号：US20100001253A1
公开(公告)日：2010-01-07
申请号：US12492618
申请日：2009-06-26
申请人： John Christopher Arnold , Lawrence Alfred Clevenger , Timothy Joseph Dalton , Michael Christopher Gaidis , Louis L. Hsu , Carl John Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： John Christopher Arnold , Lawrence Alfred Clevenger , Timothy Joseph Dalton , Michael Christopher Gaidis , Louis L. Hsu , Carl John Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power.
摘要翻译： PCM单元结构包括第一电极，相变元件和第二电极，其中相变元件插入在第一电极和第二电极之间，并且仅第一电极的周边边缘与相变元件接触，减少相变元件与第一电极之间的接触面积，从而增加通过相变元件的电流密度，并有效地在较低的电流电平和降低的编程功率下引起相变。

34. 发明授权

US07557424B2 Reversible electric fuse and antifuse structures for semiconductor devices 有权
标题翻译：用于半导体器件的可逆电熔丝和反熔丝结构
公开(公告)号：US07557424B2
公开(公告)日：2009-07-07
申请号：US11619264
申请日：2007-01-03
申请人： Keith Kwong Hon Wong , Chih-Chao Yang , Haining S Yang
发明人： Keith Kwong Hon Wong , Chih-Chao Yang , Haining S Yang
IPC分类号： H01L23/58
CPC分类号： H01L23/5256 , H01L23/5252 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating reversible fuse and antifuse structures for semiconductor devices is provided. In one embodiment, the method includes forming at least one line having a via opening for exposing a portion of a plurality of interconnect features; conformally depositing a first material layer over the via opening; depositing a second material layer over the first material layer, wherein the depositing overhangs a portion of the second material layer on a top portion of the via opening; and depositing a blanket layer of insulating material, where the depositing forms a plurality of fuse elements each having an airgap between the insulating material and the second material layer. The method further includes forming a plurality of electroplates in the insulator material connecting the fuse elements. In another embodiment, the method includes depositing a first and a second material layer on a semiconductor substrate, wherein the second material layer having a higher electrical conductivity than the first material layer; selectively etching the first and second material layer to create at least one constricted region to facilitate electromigration of the second material; wherein the electromigration creates a plurality of micro voids; and forming a plurality of electrical contacts on the second material layer.
摘要翻译：提供一种用于制造用于半导体器件的可逆熔丝和反熔丝结构的结构和方法。在一个实施例中，该方法包括形成至少一条线，其具有用于暴露多个互连特征的一部分的通孔; 在通孔开口上共形沉积第一材料层; 在所述第一材料层上沉积第二材料层，其中所述沉积在所述通孔开口的顶部部分上突出所述第二材料层的一部分; 以及沉积绝缘材料的覆盖层，其中所述沉积形成多个熔丝元件，每个熔丝元件在所述绝缘材料和所述第二材料层之间具有气隙。该方法还包括在连接熔丝元件的绝缘体材料中形成多个电镀层。在另一个实施例中，该方法包括在半导体衬底上沉积第一和第二材料层，其中第二材料层具有比第一材料层更高的导电性; 选择性地蚀刻第一和第二材料层以产生至少一个收缩区域以促进第二材料的电迁移; 其中所述电迁移产生多个微空隙; 以及在所述第二材料层上形成多个电接触。

35. 发明授权

US07544608B2 Porous and dense hybrid interconnect structure and method of manufacture 失效
标题翻译：多孔密集混合互连结构及制造方法
公开(公告)号：US07544608B2
公开(公告)日：2009-06-09
申请号：US11458464
申请日：2006-07-19
申请人： Chih-Chao Yang , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/53295 , H01L21/7682 , H01L21/76835 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense dielectric over the areas that require high mechanical strength and curing unmasked areas of the dense dielectric to burn out porogens inside the dense dielectric and transform the unmasked areas of the dense dielectric to porous dielectric material. A semiconductor structure comprises porous and dense hybrid interconnects for high performance and reliability semiconductor applications.
摘要翻译：一种用于制造结构的方法包括在整个晶片上沉积致密电介质，其包括需要低介电电容的区域和需要高机械强度的区域。该方法还包括在需要高机械强度的区域和致密电介质的固化未掩蔽区域的区域上掩蔽致密电介质的区域，以烧尽致密电介质内的致孔剂，并将致密电介质的未掩模区域转化为多孔电介质材料。半导体结构包括用于高性能和可靠性半导体应用的多孔和致密的混合互连。

36. 发明授权

US07531407B2 Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same 失效
标题翻译：具有高Q晶片背面电感器的半导体集成电路器件及其制造方法
公开(公告)号：US07531407B2
公开(公告)日：2009-05-12
申请号：US11488242
申请日：2006-07-18
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/8234
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面上的高Q片上电感器，并且使用晶片间互连连接到芯片前端的集成电路。例如，具有背面集成电感器的半导体器件包括半导体衬底，其具有插入在衬底的前侧和后侧之间的前侧，后侧和掩埋绝缘层。在半导体衬底的前侧形成集成电路，在半导体衬底的背面形成集成电感器。通过埋层绝缘层形成互连结构，将集成电感器连接到集成电路。半导体衬底可以是SOI（绝缘体上硅）结构。

37. 发明申请

US20080293257A1 DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE 失效
标题翻译：双层封装层互连结构
公开(公告)号：US20080293257A1
公开(公告)日：2008-11-27
申请号：US12186923
申请日：2008-08-06
申请人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
IPC分类号： H01L21/768
CPC分类号： H01L21/76829 , H01L21/76834 , Y10S438/927
摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.
摘要翻译： Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。高拉伸电介质膜通过沉积多层薄的电介质材料形成，每个层的厚度在约50埃以下。每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。

38. 发明申请

US20080020488A1 Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same 失效
标题翻译：具有高Q晶片背面电感器的半导体集成电路器件及其制造方法
公开(公告)号：US20080020488A1
公开(公告)日：2008-01-24
申请号：US11488242
申请日：2006-07-18
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面上的高Q片上电感器，并且使用晶片间互连连接到芯片前端的集成电路。例如，具有背面集成电感器的半导体器件包括半导体衬底，其具有插入在衬底的前侧和后侧之间的前侧，后侧和掩埋绝缘层。在半导体衬底的前侧形成集成电路，在半导体衬底的背面形成集成电感器。通过埋层绝缘层形成互连结构，将集成电感器连接到集成电路。半导体衬底可以是SOI（绝缘体上硅）结构。

39. 发明授权

US08546209B1 Replacement metal gate processing with reduced interlevel dielectric layer etch rate 失效
标题翻译：替代金属栅极处理，具有降低的层间电介质层蚀刻速率
公开(公告)号：US08546209B1
公开(公告)日：2013-10-01
申请号：US13524576
申请日：2012-06-15
申请人： Kangguo Cheng , Junli Wang , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Kangguo Cheng , Junli Wang , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor device structure includes forming an interlevel dielectric (ILD) layer over a semiconductor substrate and a dummy transistor gate structure formed on the substrate; infusing a shallow gas cluster ion beam (GCIB) layer in a top portion of the ILD layer; and removing at least one layer from the dummy transistor gate structure, wherein the at least one layer comprises a same material as the ILD layer and wherein the GCIB layer has a slower etch rate with respect to the ILD layer.
摘要翻译：形成半导体器件结构的方法包括在半导体衬底上形成层间电介质（ILD）层，以及在衬底上形成的虚设晶体管栅极结构; 在浅层气体簇离子束（GCIB）层中注入ILD层的顶部; 以及从所述虚拟晶体管栅极结构去除至少一个层，其中所述至少一个层包含与所述ILD层相同的材料，并且其中所述GCIB层相对于所述ILD层具有较慢的蚀刻速率。

40. 发明申请

US20130071998A1 Electrical Fuse With Metal Line Migration 审中-公开
标题翻译：具有金属线迁移的电气保险丝
公开(公告)号：US20130071998A1
公开(公告)日：2013-03-21
申请号：US13234205
申请日：2011-09-16
申请人： Baozhen Li , Yan Zun Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Baozhen Li , Yan Zun Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/326 , H01L21/28 , H01L23/52
CPC分类号： H01L23/5256 , H01L21/326 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element.
摘要翻译：公开了一种电熔丝装置。电路装置可以包括熔丝装置，第一电路元件和第二电路元件。熔丝包括具有第一电迁移电阻的第一触点，具有第二电迁移电阻的第二触点和耦合到第一触点和第二触点的金属线，其具有低于第二次电迁移阻力。第一电路元件耦合到第一触点，而第二电路元件耦合到第二触点。保险丝被配置为通过金属线将编程电流从第一触点传导到第二触点。此外，编程电流使金属线电离远离第二触点，以将第二电路元件与第一电路元件电隔离。

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