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    • 39. 发明申请
    • Power and ground buss layout for reduced substrate size
    • 电源和接地总线布局,以减小基板尺寸
    • US20060066681A1
    • 2006-03-30
    • US10956939
    • 2004-09-30
    • David KingKristi Rowe
    • David KingKristi Rowe
    • B41J2/05
    • B41J2/04541B41J2/04548B41J2/04563B41J2/0458B41J2/14072B41J2/14129
    • A semiconductor substrate for a micro-fluid ejection device. The substrate includes plurality of micro-fluid ejection actuators disposed adjacent a fluid supply slot in the semiconductor substrate. A plurality of power transistors, occupying a power transistor active area of the substrate, are disposed adjacent the ejection actuators and are connected through a first metal conductor layer to the ejection actuators. An array of logic circuits, occupying a logic circuit area of the substrate, is disposed adjacent the plurality of power transistors and is connected through a polysilicon conductor layer to the power transistors. A power conductor and a ground conductor for the ejection actuators is routed in a second metal conductor layer. The power conductor overlaps at least a portion of the power transistor active area of the substrate and the ground conductor overlaps at least a portion of the logic circuit area of the substrate.
    • 一种用于微流体喷射装置的半导体衬底。 衬底包括邻近半导体衬底中的流体供应槽设置的多个微流体喷射致动器。 占据基板的功率晶体管有源区的多个功率晶体管被设置在喷射致动器附近,并且通过第一金属导体层连接到喷射致动器。 占据基板的逻辑电路区域的逻辑电路阵列被布置成与多个功率晶体管相邻,并且通过多晶硅导体层连接到功率晶体管。 用于喷射致动器的电源导体和接地导体在第二金属导体层中布线。 电源导体与衬底的功率晶体管有源区域的至少一部分重叠,并且接地导体与衬底的逻辑电路区域的至少一部分重叠。