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31. 发明申请

US20060202286A1 Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device 失效
公开(公告)号：US20060202286A1
公开(公告)日：2006-09-14
申请号：US11418024
申请日：2006-05-05
申请人： Hiraku Chakihara , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
发明人： Hiraku Chakihara , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
IPC分类号： H01L29/76
CPC分类号： H01L29/6675 , H01L21/823885 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/7833 , H01L29/78642
摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

32. 发明授权

US06878703B2 Pharmaceutical composition 失效
标题翻译：药物组成
公开(公告)号：US06878703B2
公开(公告)日：2005-04-12
申请号：US10442874
申请日：2003-05-20
申请人： Toshio Sada , Makoto Mizuno
发明人： Toshio Sada , Makoto Mizuno
IPC分类号： A61K31/4178 , A61K31/54 , A61K45/06 , A61P9/12 , A61K31/41
CPC分类号： A61K45/06 , A61K31/4178 , A61K31/54 , A61K2300/00
摘要： A pharmaceutical composition comprises an angiotensin II receptor antagonist selected from among compounds having the following formula (I), a pharmacologically acceptable salt thereof, a pharmacologically acceptable ester thereof and a pharmacologically acceptable salt of such ester, and one or more diuretics: The pharmaceutical composition of the present invention has an excellent hypotensive effect and low toxicity, and therefore is useful as a medicament for preventing or treating hypertension or heart disease.
摘要翻译：药物组合物包含选自具有下式（I）的化合物，其药理学上可接受的盐，其药理学可接受的酯和该药学上可接受的盐的一种或多种利尿剂的血管紧张素II受体拮抗剂：药物组合物本发明具有优异的降血压效果和低毒性，因此可用作预防或治疗高血压或心脏病的药物。

33. 发明授权

US6049132A Multiple metallization structure for a reflection type liquid crystal display 失效
标题翻译：用于反射型液晶显示器的多金属化结构
公开(公告)号：US6049132A
公开(公告)日：2000-04-11
申请号：US893671
申请日：1997-07-11
申请人： Masanori Iwahashi , Makoto Mizuno , Koji Hanihara
发明人： Masanori Iwahashi , Makoto Mizuno , Koji Hanihara
IPC分类号： G02F1/1362 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： G02F1/136277 , G02F1/136227 , H01L23/53223 , H01L23/53242 , H01L23/53247 , H01L23/53257 , H01L2924/0002
摘要： In a semiconductor chip for Si chip based liquid crystal having insulating films and interconnection layers formed on a semiconductor substrate, a thin interconnection layer made of TiN/Ti having strong erosion resistance is formed on an uppermost interlayer insulating film having a flat surface to substantially expose the thin uppermost interconnection layer to the surface of the chip, the uppermost insulating film is covered with a protection film made of p-SiN and a thin insulating film having a mirror-like flat surface is formed on the uppermost interconnection layer.
摘要翻译：在具有形成在半导体衬底上的绝缘膜和互连层的用于Si芯片的液晶的半导体芯片中，在具有平坦表面的最上层的层间绝缘膜上形成具有很强的耐腐蚀性的由TiN / Ti制成的薄互连层，以基本上露出在芯片表面的最薄的最上层的互连层，最上层的绝缘膜被由p-SiN制成的保护膜覆盖，并且在最上层的互连层上形成了具有镜面平坦表面的薄绝缘膜。

34. 发明授权

US5391509A Method of manufacturing a semiconductor device forming a high concentration impurity region through a CVD insulating film 失效
标题翻译：通过CVD绝缘膜制造形成高浓度杂质区的半导体器件的方法
公开(公告)号：US5391509A
公开(公告)日：1995-02-21
申请号：US164954
申请日：1993-12-10
申请人： Naoki Matsukawa , Makoto Mizuno , Katsuhiro Shimazu
发明人： Naoki Matsukawa , Makoto Mizuno , Katsuhiro Shimazu
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/2652
摘要： Impurities are introduced into a semiconductor substrate by using a gate electrode formed on the semiconductor substrate through an oxide film as a mask, and low concentration impurity regions are formed. Then, side walls are formed on the gate electrode. Next, after an insulating film is formed on the whole surface of the substrate by a CVD method, impurities are introduced by using the gate electrode and the side walls as a mask, and high concentration impurity regions are formed. Then, a thermal treatment of the substrate is performed, and after the low concentration impurity regions and the high concentration impurity regions are crystallized, an interlayer insulating film is formed.
摘要翻译：通过使用通过氧化膜形成在半导体衬底上的栅电极作为掩模，将杂质引入到半导体衬底中，形成低浓度杂质区。然后，在栅电极上形成侧壁。接下来，在通过CVD法在基板的整个表面上形成绝缘膜之后，通过使用栅电极和侧壁作为掩模来引入杂质，形成高浓度杂质区。然后，进行基板的热处理，在低浓度杂质区域和高浓度杂质区域结晶后，形成层间绝缘膜。

35. 发明授权

US4970952A Date-stamping apparatus 失效
标题翻译：日期冲压装置
公开(公告)号：US4970952A
公开(公告)日：1990-11-20
申请号：US479357
申请日：1990-02-13
申请人： Imao Hiraga , Masamori Uchikawa , Makoto Mizuno
发明人： Imao Hiraga , Masamori Uchikawa , Makoto Mizuno
IPC分类号： B41K3/10 , B41K1/10 , B41K1/14
CPC分类号： B41K1/10
摘要： A date-stamping apparatus having a casing, a bridge member located at the lower end of the casing, a tension roller located above the casing and forced upwardly, an endless date-printing belt having printing letters on its outside surface and spanned between the bridge member and the tension roller, a date-belt driving wheel located within the casing at a substantially intermediate portion. The date of driving wheel has a circumferential engagement section co-operating with the belt and being contacted by the outside surface of the belt, and an electric motor intermittently energized by a timing circuit and operatively connected with the belt-driving wheel, so that stamped date is electrically adjusted.
摘要翻译：具有壳体的日期冲压装置，位于壳体下端的桥接构件，位于壳体上方并被向上推动的张紧辊，在其外表面上具有打印字母并跨越桥的无端日历打印带构件和张紧辊，位于壳体内的大致中间部分的日期带驱动轮。驱动轮的日期具有与皮带合作并与皮带的外表面接触的圆周接合部分，以及由定时电路间歇地通电并与皮带驱动轮可操作地连接的电动机，使得冲压日期电气调整。

36. 外观设计

USD268598S Felt pen 失效
公开(公告)号：USD268598S
公开(公告)日：1983-04-12
申请号：US206978
申请日：1980-11-14
申请人： Takeshi Mizutani , Makoto Mizuno
设计人： Takeshi Mizutani , Makoto Mizuno

37. 发明授权

US08576634B2 Semiconductor device comprising a memory cell group having a gate width larger than a second memory cell group 有权
标题翻译：半导体器件包括具有大于第二存储单元组的栅极宽度的存储单元组
公开(公告)号：US08576634B2
公开(公告)日：2013-11-05
申请号：US12764090
申请日：2010-04-20
申请人： Fumitoshi Ito , Yoshiyuki Kawashima , Takeshi Sakai , Yasushi Ishii , Yasuhiro Kanamaru , Takashi Hashimoto , Makoto Mizuno , Kousuke Okuyama , Yukiko Manabe
发明人： Fumitoshi Ito , Yoshiyuki Kawashima , Takeshi Sakai , Yasushi Ishii , Yasuhiro Kanamaru , Takashi Hashimoto , Makoto Mizuno , Kousuke Okuyama , Yukiko Manabe
IPC分类号： G11C11/34 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0466 , H01L21/28282 , H01L27/115 , H01L29/42344 , H01L29/66833 , H01L29/792
摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.
摘要翻译：改善了具有非易失性存储元件的半导体器件的积分度和重写次数。与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。

38. 发明授权

US08174707B2 Optical element positioning apparatus 失效
标题翻译：光学元件定位装置
公开(公告)号：US08174707B2
公开(公告)日：2012-05-08
申请号：US12270287
申请日：2008-11-13
申请人： Makoto Mizuno
发明人： Makoto Mizuno
IPC分类号： G01B11/14
CPC分类号： G02B7/005 , G02B13/143 , G02B17/0657 , G03F7/70258
摘要： An optical element positioning apparatus of the present invention includes a moving unit including an optical element 2, a drive mechanism 100 configured to drive the moving unit, a position measuring sensor 130 configured to measure a position of the optical element 2, and an optical element controller 10 configured to control the drive mechanism 100 based on a measurement result by the position measuring sensor 130. An incident position (p point) at which a principal ray of a central field enters the optical element 2 is displaced from an optical axis of an optical system including the optical element 2, and the position measuring sensor 130 measures the incident position in an optical axis direction.
摘要翻译：本发明的光学元件定位装置包括：移动单元，包括光学元件2，构造成驱动移动单元的驱动机构100，被配置为测量光学元件2的位置的位置测量传感器130;以及光学元件控制器10构造成基于位置测量传感器130的测量结果来控制驱动机构100.中心场的主射线进入光学元件2的入射位置（p点）从光学元件2的光轴位移包括光学元件2的光学系统和位置测量传感器130测量光轴方向上的入射位置。

39. 发明授权

US07957195B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07957195B2
公开(公告)日：2011-06-07
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

40. 发明授权

US07821726B2 Optical element positioning apparatus, projection optical system and exposure apparatus 有权
标题翻译：光学元件定位装置，投影光学系统和曝光装置
公开(公告)号：US07821726B2
公开(公告)日：2010-10-26
申请号：US12171644
申请日：2008-07-11
申请人： Ryo Nawata , Makoto Mizuno , Shigeyuki Uzawa
发明人： Ryo Nawata , Makoto Mizuno , Shigeyuki Uzawa
IPC分类号： G02B7/02
CPC分类号： G02B7/005 , G02B7/1827 , G03F7/70258 , G03F7/70825
摘要： An optical element is moved in six-degrees-of-freedom. Three first displacement sensors are disposed on a base plate and measure respective displacement amounts of three mutually different points on the optical element in a first direction. A second displacement sensor measures a displacement amount of one point on the optical element in a second direction. Two third displacement sensors measure respective displacement amounts of two mutually different points on the optical element in a third direction. A transformation processor transforms the six measured displacement amounts. A calibration processor calibrates the transformed displacement amounts with a calibration matrix of which coefficients are previously obtained to calibrate the displacement amounts in the six-degrees-of-freedom, which have errors due to measurement errors of the displacement sensors. A controller outputs command values based on differences between the calibrated displacement amounts and target displacement amounts.
摘要翻译：光学元件以6自由度移动。三个第一位移传感器设置在基板上，并且在第一方向上测量光学元件上的三个相互不同的点的相应位移量。第二位移传感器在第二方向上测量光学元件上的一个点的位移量。两个第三位移传感器在第三方向测量光学元件上的两个相互不同的点的相应位移量。变换处理器转换六个测量的位移量。校准处理器使用预先获得系数的校准矩阵校准变换的位移量，以校准六自由度中的位移量，其由于位移传感器的测量误差而具有误差。控制器基于校准的位移量和目标位移量之间的差异输出命令值。

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