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31. 发明授权

US5691231A Method of manufacturing silicon on insulating substrate 失效
标题翻译：在绝缘基板上制造硅的方法
公开(公告)号：US5691231A
公开(公告)日：1997-11-25
申请号：US779226
申请日：1997-01-07
申请人： Kenya Kobayashi , Tomohiro Hamajima , Kensuke Okonogi
发明人： Kenya Kobayashi , Tomohiro Hamajima , Kensuke Okonogi
IPC分类号： H01L21/20 , H01L21/762 , H01L21/76
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76286 , Y10S148/012
摘要： A first silicon single crystal substrate and a second silicon single crystal substrate are bonded together and the first silicon single crystal substrate is formed thin as an SOI layer. An insulation film is buried in portions of the bonding surface of one of the two silicon single crystal substrates, and in addition, a polycrystal silicon layer is formed on the bonding surface of the silicon single crystal substrate on the side into which the insulation film is buried.
摘要翻译：第一硅单晶衬底和第二硅单晶衬底被结合在一起，并且第一硅单晶衬底被形成为薄的SOI层。在两个硅单晶衬底之一的接合表面的部分中埋设有绝缘膜，此外，在单晶硅衬底的绝缘膜的一侧的接合面上形成多晶硅层埋葬

32. 发明授权

US5529947A Semiconductor device with clad substrate and fabrication process therefor 失效
标题翻译：具有复合衬底的半导体器件及其制造工艺
公开(公告)号：US5529947A
公开(公告)日：1996-06-25
申请号：US356509
申请日：1994-12-15
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/02 , H01L21/76 , H01L21/762 , H01L27/12 , H01L21/302 , H01L21/304 , H01L21/306
CPC分类号： H01L21/76 , H01L21/76264 , H01L21/76275 , H01L21/76286
摘要： On a first surface of a first single crystal silicon substrate, in which a silicon dioxide layer having gradually tapered peripheral edge (tapered wall), a second single crystal silicon substrate is clad. On the second surface of the first single crystal silicon substrate, an island form polycrystalline silicon region is isolated from remaining region by an isolation groove to form an element. By reducing step between the buried silicon dioxide layer and the first single crystal silicon substrate, local concentration of a stress can be successfully avoided. Also, abrasion of the silicon oxide layer and single crystal silicon substrate having mutually different etching speeds is not performed so that the step can be lowered to eliminate formation of void. Between the first surface of the first single crystal silicon substrate formed with the elements and the cladding surface, the silicon dioxide layer is present to avoid influence of contaminant penetrating during cladding process. Accordingly, degradation of reliability due to stress concentration and formation of void, and contamination in the SOI clad substrate can be successfully avoided.
摘要翻译：在第一单晶硅衬底的第一单面硅衬底的第二表面上，其中具有逐渐变细的周缘（锥形壁）的二氧化硅层，第二单晶硅衬底被包层。在第一单晶硅衬底的第二表面上，岛状多晶硅区域通过隔离沟槽与剩余区域隔离以形成元件。通过减少掩埋二氧化硅层和第一单晶硅衬底之间的步骤，可以成功地避免局部应力集中。此外，不进行具有相互不同蚀刻速度的氧化硅层和单晶硅衬底的磨损，从而可以降低该步骤以消除空隙的形成。在形成有元件的第一单晶硅衬底的第一表面和包层表面之间，存在二氧化硅层以避免包覆过程中污染物穿透的影响。因此，可以成功地避免由于应力集中和形成空穴引起的可靠性的劣化以及SOI包覆衬底中的污染。

33. 发明授权

US07737505B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US07737505B2
公开(公告)日：2010-06-15
申请号：US11859043
申请日：2007-09-21
申请人： Kensuke Okonogi , Kiyonori Ohyu
发明人： Kensuke Okonogi , Kiyonori Ohyu
IPC分类号： H01L29/78 , H01L23/52
CPC分类号： H01L29/7834 , H01L21/26506 , H01L21/28525 , H01L21/76843 , H01L21/76859 , H01L23/53271 , H01L29/66628 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.
摘要翻译：半导体器件可以包括但不限于单晶硅扩散层，多晶硅导体和扩散阻挡层。扩散阻挡层将多晶硅导体与单晶硅扩散层分离。扩散阻挡层防止在单晶硅扩散层和多晶硅导体之间的硅间隙和硅空位中的至少一个的扩散。

34. 发明授权

US07700431B2 Method for manufacturing a semiconductor device having polysilicon plugs 失效
标题翻译：制造具有多晶硅插头的半导体器件的方法
公开(公告)号：US07700431B2
公开(公告)日：2010-04-20
申请号：US11153321
申请日：2005-06-16
申请人： Kensuke Okonogi , Kiyonori Ohyu , Kazutaka Manabe , Satoru Yamada , Takuo Ohashi
发明人： Kensuke Okonogi , Kiyonori Ohyu , Kazutaka Manabe , Satoru Yamada , Takuo Ohashi
IPC分类号： H01L21/8242 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/26513 , H01L21/28525 , H01L21/324 , H01L21/76877 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L27/10894 , H01L29/66575
摘要： A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.
摘要翻译：一种用于在硅衬底上制造DRAM器件的方法包括：在存储单元区域中形成单元晶体管和在外围电路区域中形成其它晶体管; 形成连接到所述单元晶体管的扩散区域的多晶硅插塞和连接到所述另一晶体管的扩散区域的金属插塞; 在980〜1020℃的温度下进行热处理。在700〜850℃的温度下进行热处理。将氟或氟化硼注入其他晶体管的扩散区域; 并在500〜850℃的温度下进行热处理。

35. 发明申请

US20050282335A1 Method for manufacturing a semiconductor device having polysilicon plugs 失效
标题翻译：制造具有多晶硅插头的半导体器件的方法
公开(公告)号：US20050282335A1
公开(公告)日：2005-12-22
申请号：US11153321
申请日：2005-06-16
申请人： Kensuke Okonogi , Kiyonori Ohyu , Kazutaka Manabe , Satoru Yamada , Takuo Ohashi
发明人： Kensuke Okonogi , Kiyonori Ohyu , Kazutaka Manabe , Satoru Yamada , Takuo Ohashi
IPC分类号： H01L21/265 , H01L21/285 , H01L21/324 , H01L21/336 , H01L21/768 , H01L21/8242
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/26513 , H01L21/28525 , H01L21/324 , H01L21/76877 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L27/10894 , H01L29/66575
摘要： A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.
摘要翻译：在硅衬底上制造DRAM器件的方法包括：在存储单元区域中形成单元晶体管和外围电路区域中的其它晶体管; 形成连接到所述单元晶体管的扩散区域的多晶硅插塞和连接到所述另一晶体管的扩散区域的金属插塞; 在980〜1020℃的温度下进行热处理。在700〜850℃的温度下进行热处理。将氟或氟化硼注入其他晶体管的扩散区域; 并在500〜850℃的温度下进行热处理。

36. 发明授权

US6004406A Silicon on insulating substrate 失效
标题翻译：绝缘基板上的硅
公开(公告)号：US6004406A
公开(公告)日：1999-12-21
申请号：US490351
申请日：1995-06-14
申请人： Kenya Kobayashi , Tomohiro Hamajima , Kensuke Okonogi
发明人： Kenya Kobayashi , Tomohiro Hamajima , Kensuke Okonogi
IPC分类号： H01L21/20 , H01L21/762 , H01L49/02 , H01L29/06
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76286 , Y10S148/012
摘要： A first silicon single crystal substrate and a second silicon single crystal substrate are bonded together and the first silicon single crystal substrate is formed thin as an SOI layer. An insulation film is buried in portions of the bonding surface of one of the two silicon single crystal substrates, and in addition, a polycrystal silicon layer is formed on the bonding surface of the silicon single crystal substrate on the side into which the insulation film is buried.
摘要翻译：第一硅单晶衬底和第二硅单晶衬底被结合在一起，并且第一硅单晶衬底被形成为薄的SOI层。在两个硅单晶衬底之一的接合表面的部分中埋设有绝缘膜，此外，在单晶硅衬底的绝缘膜的一侧的接合面上形成多晶硅层埋葬

37. 发明授权

US5872388A Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5872388A
公开(公告)日：1999-02-16
申请号：US21394
申请日：1998-02-10
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/762 , H01L21/18 , H01L21/20 , H01L21/76 , H01L29/00
CPC分类号： H01L21/185 , H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76283 , H01L21/76286
摘要： A semiconductor device having a bonded wafer structure capable of reducing crystal defect in a power element forming region thereof is disclosed. A recess is formed in a control circuit element forming region of a first n- silicon substrate, then filled with a silicon oxide film and subjected to grinding and polishing to provide a mirror-surface. An n- epitaxial layer is formed on the surface of a second n+ silicon substrate, then the surface of the epitaxial layer is coupled to the surfaces of the silicon oxide film and second circuit region of the first substrate and heat-treated to be bonded thereto.
摘要翻译：公开了一种具有能够减少其功率元件形成区域中的晶体缺陷的键合晶片结构的半导体器件。在第一n-硅衬底的控制电路元件形成区域中形成凹部，然后填充氧化硅膜并进行研磨抛光以提供镜面。在第二n +硅衬底的表面上形成n外延层，然后将外延层的表面耦合到第一衬底的氧化硅膜和第二电路区的表面，并进行热处理以与其结合。

38. 发明授权

US5849102A Method of cleaning a surface of a semiconductor substrate by a heat treatment in an inert gas atmosphere 失效
标题翻译：通过在惰性气体气氛中的热处理来清洁半导体衬底的表面的方法
公开(公告)号：US5849102A
公开(公告)日：1998-12-15
申请号：US808169
申请日：1997-02-28
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/205 , H01L21/00 , H01L21/304 , H01L21/306 , H01L27/12 , B08B7/04
CPC分类号： H01L21/02046 , H01L21/6704 , H01L21/67069 , H01L21/67098 , Y10S134/902 , Y10S438/906
摘要： A method of cleaning a surface of a semiconductor comprising the steps of a) washing the semiconductor surface with chemicals to remove particles and metal impurities from the surface; b) inserting the semiconductor into a furnace that contains a gas mixture of nitrogen gas and a second inert gas; c) replacing the gas mixture with a third inert gas; d) heating the furnace containing the third inert gas for a predetermined period of time; and e) replacing the third inert gas in the furnace with oxygen and thermally oxidizing the surface of the semiconductor to form an oxide film on the surface.
摘要翻译：一种清洁半导体表面的方法，包括以下步骤：a）用化学品洗涤半导体表面以从表面去除颗粒和金属杂质; b）将半导体插入含有氮气和第二惰性气体的气体混合物的炉中; c）用第三惰性气体代替气体混合物; d）将含有第三惰性气体的炉子加热预定的时间; 和e）用氧代替炉中的第三惰性气体，并热氧化半导体的表面以在表面上形成氧化膜。

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