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31. 发明申请

US20070205384A1 Flow Rate Control Apparatus 审中-公开
标题翻译：流量控制装置
公开(公告)号：US20070205384A1
公开(公告)日：2007-09-06
申请号：US11672295
申请日：2007-02-07
申请人： Kenichi Kurosawa
发明人： Kenichi Kurosawa
IPC分类号： F16K47/00 , F16K15/00 , B05B1/14
CPC分类号： F16K11/22 , F15B13/081 , F15B13/0814 , F15B13/0835 , F15B13/0857 , F15B13/086 , F15B13/0889 , F15B13/0896 , F16K27/0263 , F16K27/029 , Y10T137/7722
摘要： A flow rate control apparatus includes a base section, wherein the base section is composed of a plurality of stacked metal plates. The flow rate control apparatus further includes a pressure control section, which regulates pressure of a pressure fluid (gas) that flows through a first passage in the base section, a pressure sensor that detects pressure of the pressure fluid flowing through a second passage, and a flow passage-switching section, including first to third orifices, for throttling the fluid pressure-regulated by the pressure control section so as to have a predetermined flow rate, and which has first to third ON/OFF valves for switching fourth to sixth passages for respectively directing the pressure fluid toward a pressure fluid output port.
摘要翻译：一种流量控制装置，包括基部，其中所述基部由多个堆叠的金属板构成。所述流量控制装置还包括：压力控制部，其调节流过所述基部的第一通路的压力流体（气体）的压力;检测压力流体流过第二通路的压力的压力传感器;以及流路切换部，包括第一至第三孔，用于节流由压力控制部压力调节的流体以具有预定流量，并且具有用于切换第四至第六通道的第一至第三导通/截止阀用于分别将压力流体引向压力流体输出端口。

32. 发明授权

US6038615A Input/output device for connection and disconnection of active lines 失效
标题翻译：用于连接和断开有源线路的输入/输出设备
公开(公告)号：US6038615A
公开(公告)日：2000-03-14
申请号：US43517
申请日：1998-03-23
申请人： Tsutomu Yamada , Kenichi Kurosawa , Yasuo Kaminaga , Kouji Masui , Akihiro Ohashi
发明人： Tsutomu Yamada , Kenichi Kurosawa , Yasuo Kaminaga , Kouji Masui , Akihiro Ohashi
IPC分类号： G06F1/18 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4081 , G06F1/189 , Y02B60/1228 , Y02B60/1235
摘要： There is provided an input/output device which is capable of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal thereof. An expansion device 800 includes an electronic circuit 400 and a MOS switch 300 and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 is coupled to two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state; and, inside the expansion device, the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260. At the time of insertion or removal, adverse influence is not exerted on the signal transmission on the system bus, and effects of load variation on the main power supply are reduced.
摘要翻译： PCT No.PCT / JP95 / 01955 Sec。 371日期：1998年3月23日 102（e）1998年3月23日PCT PCT 1995年9月27日PCT公布。公开号WO97 / 12312 PCT 日期1997年4月3日提供了一种输入/输出装置，其能够在插入或移除系统总线时不对连接到系统总线的其它扩展装置施加任何不利影响。扩展装置800包括电子电路400和MOS开关300，并通过具有长和短引脚的连接器连接到系统总线（BUS）。扩展装置800耦合到两个电源系统，即稳定的电源250和不稳定的电源260.在插入或移除扩展装置800时，向MOS开关300提供电力，并且高阻抗通过一对长引脚保持来自稳定电源的电路，以便可靠地将MOS开关300置于高阻抗状态; 并且在扩展装置内部，高阻抗保持电路350驱动开/关控制端子，并且从不稳定电源260向电子电路400提供电力。在插入或移除时不会产生不利影响对系统总线上的信号传输，负载变化对主电源的影响减小。

33. 发明授权

US5841963A Dual information processing system having a plurality of data transfer channels 失效
标题翻译：双信息处理系统具有多个数据传输通道
公开(公告)号：US5841963A
公开(公告)日：1998-11-24
申请号：US861471
申请日：1997-05-21
申请人： Tetsuaki Nakamikawa , Shin Kokura , Kenichi Kurosawa , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Hiroshi Ohguro
发明人： Tetsuaki Nakamikawa , Shin Kokura , Kenichi Kurosawa , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Hiroshi Ohguro
IPC分类号： G06F11/16 , G06F15/17
CPC分类号： G06F11/1658
摘要： A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.
摘要翻译：由由多个数据传送单元连接的两个计算机系统和用于存储器副本的多个数据传送通道组成的双计算机系统，使得在从故障恢复时再次同步计算机系统。当数据传输通道没有发生故障时，数据传输单元在存储器复制操作中共享数据传输的负载，并且当在存储器复制操作期间在任何数据传送单元发生故障时，使用剩余的正常数据传送单元再次传送数据，从而高速地进行存储器复制，以便在从故障恢复时再次同步计算机系统，并且提高从故障恢复时的系统可靠性。

34. 发明授权

US08774162B2 Real time control network system 有权
标题翻译：实时控制网络系统
公开(公告)号：US08774162B2
公开(公告)日：2014-07-08
申请号：US13131512
申请日：2009-11-25
申请人： Kunihiko Tsunedomi , Kenichi Kurosawa
发明人： Kunihiko Tsunedomi , Kenichi Kurosawa
IPC分类号： H04J3/06 , H04L12/413
CPC分类号： H04L12/403 , H04L2012/40241 , H04L2012/40273
摘要： Provided is an on-vehicle network which can improve the network use efficiency and reduce the controller processor overhead even when the same communication cycle as the frame cannot be set in the filtering condition of a communication control device. A reference signal transmission controller is arranged in a network so as to generate and transmit a reference signal in accordance with the communication cycle. A reference signal reception controller receives the reference signal and compares the reference signals to a predetermined filtering condition table. If the signal is matched with the table, the controller executes a data reception process and a data transmission process.
摘要翻译：提供了一种车载网络，即使在与通信控制装置的过滤条件不相关的通信周期的情况下，也能够提高网络使用效率并降低控制器处理器开销。参考信号传输控制器被布置在网络中，以便根据通信周期生成和发送参考信号。参考信号接收控制器接收参考信号并将参考信号与预定的滤波条件表进行比较。如果信号与表匹配，则控制器执行数据接收处理和数据发送处理。

35. 发明授权

US06289407B1 Input/output device for connection and disconnection of active lines 有权
标题翻译：用于连接和断开有源线路的输入/输出设备
公开(公告)号：US06289407B1
公开(公告)日：2001-09-11
申请号：US09499897
申请日：2000-02-08
申请人： Tsutomu Yamada , Kenichi Kurosawa , Yasuo Kaminaga , Kouji Masui , Akihiro Ohashi
发明人： Tsutomu Yamada , Kenichi Kurosawa , Yasuo Kaminaga , Kouji Masui , Akihiro Ohashi
IPC分类号： G06F1300
CPC分类号： G06F13/4081 , G06F1/189 , Y02D10/14 , Y02D10/151
摘要： There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260. At the time of insertion or removal, adverse influence is not exerted on the signal transmission on the system bus, and effects of load variation on the main power supply are reduced.
摘要翻译：提供了一种输入/输出装置，其在插入或移除时对连接到系统总线的其它扩展装置没有任何不利影响。扩展装置800包括电子电路400和MOS开关300，并且经由具有长和短引脚的连接器连接到系统总线（BUS）。膨胀装置800是两个电源系统，即稳定的电源250和不稳定的电源260.在插入或移除扩展装置800时，向MOS开关300提供电力和高阻抗保持电路通过一对长引脚稳定供电，为了可靠地将MOS开关300置于高阻抗状态，高阻抗保持电路350在扩展装置的内部驱动开/关控制端子，并且向来自不稳定电源260的电子电路400.在插入或移除时，不会对系统总线上的信号传输产生不利影响，并且降低对主电源的负载变化的影响。

36. 发明授权

US06249363B1 Optical communication method, optical linking device and optical communication system 失效
标题翻译：光通信方法，光连接装置和光通信系统
公开(公告)号：US06249363B1
公开(公告)日：2001-06-19
申请号：US09115763
申请日：1998-07-15
申请人： Hiroshi Arita , Tetsuaki Nakamikawa , Kenichi Kurosawa , Hiroaki Fukumaru , Hisao Ogawa
发明人： Hiroshi Arita , Tetsuaki Nakamikawa , Kenichi Kurosawa , Hiroaki Fukumaru , Hisao Ogawa
IPC分类号： H04B1020
CPC分类号： H04B10/271 , G06F13/4022 , H04B10/27 , H04B10/278
摘要： The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.
摘要翻译：该系统包括用于在所述电气总线未被驱动（OFF模式）下观察所述电动总线的模式和所述光纤的模式的光学总线桥接装置，使得通过光纤连接的两条电动总线的模式为使总线同时由多个节点驱动。虽然所述电气总线中的一个或两个已经被连接到其上的节点驱动（ON模式），但是已经从被驱动到所述光纤的总线连续地产生光输出，并且在从所述光纤输入光没有观察到所述总线的模式，而是向输入光的一侧的电力总线产生电力输出以驱动总线。光总线桥接装置在光总线桥接装置向光纤输出信号之后光纤在预定时间内不变化时，改变电气总线的模式。

37. 发明授权

US5748873A Fault recovering system provided in highly reliable computer system having duplicated processors 失效
标题翻译：在具有重复处理器的高度可靠的计算机系统中提供的故障恢复系统
公开(公告)号：US5748873A
公开(公告)日：1998-05-05
申请号：US686486
申请日：1996-07-26
申请人： Hiroshi Ohguro , Koichi Ikeda , Takaaki Nishiyama , Hiroshi Iwamoto , Kenichi Kurosawa , Tetsuaki Nakamikawa , Michio Morioka
发明人： Hiroshi Ohguro , Koichi Ikeda , Takaaki Nishiyama , Hiroshi Iwamoto , Kenichi Kurosawa , Tetsuaki Nakamikawa , Michio Morioka
IPC分类号： G06F11/16 , G06F11/34
CPC分类号： G06F11/165 , G06F11/1658 , G06F11/1679
摘要： A highly reliable computer system is intended to duplicate processors, compare the outputs of the processors with each other and enhance the validity of the output of processor system. If a mismatch between the outputs is detected, one of the processors performs a process of saving an internal state of the processor in amain memory and diagnosing factor of the detected mismatch. If the process is recognized to be continued in a duplex mode, the processors are re-synchronized by a processor reset, and initialize themselves and restore the internal information saved in the main memory for continuing the process having been proceeded before the fault occurred.
摘要翻译：高度可靠的计算机系统旨在复制处理器，将处理器的输出相互比较，并提高处理器系统输出的有效性。如果检测到输出之间的不匹配，则其中一个处理器执行将处理器的内部状态保存在大量存储器中并诊断检测到的失配的因素的处理。如果该处理被识别为以双工模式继续，则处理器通过处理器复位重新同步，并且自己初始化并恢复保存在主存储器中的内部信息，以便继续在故障发生之前进行的处理。

38. 发明授权

US5699541A Memory system using schottky diodes to reduce load capacitance 失效
标题翻译：使用肖特基二极管降低负载电容的存储系统
公开(公告)号：US5699541A
公开(公告)日：1997-12-16
申请号：US406147
申请日：1995-03-20
申请人： Kenichi Kurosawa , Shin Kokura , Michio Morioka , Tetsuaki Nakamikawa , Sakou Ishikawa
发明人： Kenichi Kurosawa , Shin Kokura , Michio Morioka , Tetsuaki Nakamikawa , Sakou Ishikawa
IPC分类号： G11C11/417 , G06F13/16 , G11C7/10 , G11C11/409 , G06F12/00 , G06F9/26 , G06F9/32 , G06F12/02
CPC分类号： G11C7/1051 , G11C7/1078
摘要： A computer memory system is disclosed with an input/output circuitry capable of separating the load separating the load capacitance of an output circuit of a semiconductor memory connected to a memory bus from the memory bus. In order to separate the load capacitance of a semiconductor memory connected to a memory bus signal line, a Schottky diode is arranged between the semiconductor memory and the memory bus line, and a voltage control circuit is provided to control whether a reverse bias voltage is applied to the Schottky diode. The speed of signal transmission does not decrease even when a large number of semiconductor memories are connected to the memory bus since the load capacitance of the semiconductor memories is separated from the bus. Therefore, it is possible to construct a high speed and large capacity memory system.
摘要翻译：公开了具有输入/输出电路的计算机存储器系统，该输入/输出电路能够将连接到存储器总线的半导体存储器的输出电路的负载电容与存储器总线分开。为了分离连接到存储器总线信号线的半导体存储器的负载电容，在半导体存储器和存储器总线之间布置肖特基二极管，并且提供电压控制电路以控制是否施加反向偏置电压到肖特基二极管。即使当半导体存储器的负载电容与总线分离时，即使大量的半导体存储器连接到存储器总线，信号传输的速度也不会降低。因此，可以构建高速，大容量的存储系统。

39. 发明授权

US5345560A Prefetch buffer and information processing system using the same 失效
标题翻译：预取缓冲区和信息处理系统使用相同
公开(公告)号：US5345560A
公开(公告)日：1994-09-06
申请号：US921742
申请日：1992-07-30
申请人： Shuuichi Miura , Kenichi Kurosawa , Tetsuaki Nakamikawa , Kenji Hirose
发明人： Shuuichi Miura , Kenichi Kurosawa , Tetsuaki Nakamikawa , Kenji Hirose
IPC分类号： G06F9/38 , G06F12/02 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0811 , G06F2212/6022 , G06F2212/6026
摘要： A prefetch buffer adapted to be installed between a cache memory and a main memory in a computer system having a CPU. The prefetch buffer includes a buffer storage having at least one entry for storing prefetched data and an address tag, which is to be used for searching the data, as a pair; a data searcher for searching, from the data stored in the buffer storage, for data having an address requested by the CPU; and an address estimator for determining an address of data to be prefetched next from the main memory, based on the address requested by the CPU and also on a history of the addresses of data prefetched in the past from the main memory; and an address generator for generating an address of data to be prefetched from the main memory. With this arrangement, it is possible to improve the hit ratio of the prefetch buffer regardless of the direction in which the access address varies.
摘要翻译：一种适于安装在具有CPU的计算机系统中的高速缓冲存储器和主存储器之间的预取缓冲器。预取缓冲器包括具有用于存储预取数据的至少一个条目和要用于搜索数据的地址标签作为一对的缓冲存储器; 数据搜索器，用于从存储在缓冲存储器中的数据中搜索具有由CPU请求的地址的数据; 以及地址估计器，用于基于所述CPU所请求的地址以及来自主存储器的过去预取的数据的地址的历史来确定要从主存储器预先预取的数据的地址; 以及地址发生器，用于从主存储器生成要预取的数据的地址。利用这种布置，无论访问地址变化的方向如何，都可以提高预取缓冲器的命中率。

40. 发明授权

US4912152A One-pack type thermosetting composition 失效
标题翻译：一包式热固性组合物
公开(公告)号：US4912152A
公开(公告)日：1990-03-27
申请号：US264388
申请日：1988-10-31
申请人： Kazumi Nejigaki , Kenichi Kurosawa , Isao Nishiwaki , Yukihiro Okubo
发明人： Kazumi Nejigaki , Kenichi Kurosawa , Isao Nishiwaki , Yukihiro Okubo
IPC分类号： C08G18/10 , C08G18/70
CPC分类号： C08G18/703 , C08G18/10 , C08G2190/00
摘要： A one-pack type thermosetting composition comprising (A) at least one polyisocyanate compound having dispersed therein (B) at least one compound selected from the group consisting of (1) a solid polyfunctional compound having at least one functional group selected from the group consisting of hydrazino, primary amido and sulfamoyl groups, (2) a solid compound having at least one amidino group and (3) a solid compound having a heterocyclic ring and a plurality of active hydrogen atoms, or a one-pack type thermosetting composition comprising (A') a mixture consisting of (a) at least one polyisocyanate compound and (b) at least one high boiling polar compound, having dispersed therein (B') a solid polyfunctional compound having at least one active hydrogen atom. Said one-pack type thermosetting composition is storable and suitable for use in adhesives, sealing materials, coatings and shaped articles of resin.
摘要翻译：一种单组分型热固性组合物，其包含（A）至少一种其中分散有的多异氰酸酯化合物（B）至少一种选自以下的化合物：（1）具有至少一个选自以下的官能团的固体多官能化合物：的肼基，伯酰胺基和氨磺酰基，（2）具有至少一个脒基的固体化合物和（3）具有杂环和多个活性氢原子的固体化合物，或单组分型热固性组合物，其包含（ A'）由（a）至少一种多异氰酸酯化合物和（b）至少一种分散在其中的高沸点极性化合物（B'）组成的混合物，其具有至少一个活性氢原子的固体多官能化合物。所述单组分型热固性组合物可储存并适用于粘合剂，密封材料，涂料和成型树脂制品。

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