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    • 31. 发明授权
    • Method of fabricating a semiconductor DRAM
    • 制造半导体DRAM的方法
    • US5374579A
    • 1994-12-20
    • US108518
    • 1993-08-18
    • Hideaki Kuroda
    • Hideaki Kuroda
    • H01L27/04H01L21/822H01L21/8242H01L27/10H01L27/108H01L21/70
    • H01L27/10852
    • A semiconductor DRAM comprises: a stacked capacitor (41) comprising a storage node electrode (42) a capacitor dielectric film (44) and a plate electrode (43), and formed in a memory cell area of a semiconductor substrate (11); and bit lines (18). A plate electrode forming film (53) having a portion extending over the entire memory cell area (21) or at least over an area including the plate electrode (43) and bit contact forming portions (24) in the memory cell area (21), and contact forming portions (34) in the peripheral circuit area (31) is formed, a second layer insulating film (15) is formed over the plate electrode forming film (53), bit contact holes (25) and contact holes (36) are formed respectively in the bit contact forming portions (24) and the contact forming portions (31) through the plate electrode forming film (53), the side surfaces of the bit contact holes (25) and the contact holes (36) are coated respectively with insulating films (26, 37), conductive plugs (16, 17) are formed in the bit contact holes (25) and the contact holes (36), and bit lines (18) are formed on the second layer insulating film (15) so as to be connected to the conductive plugs (16, 17).
    • 半导体DRAM包括:层叠电容器(41),包括存储节点电极(42),电容器电介质膜(44)和平板电极(43),并形成在半导体衬底(11)的存储单元区域中。 和位线(18)。 一种板状电极形成膜(53),其具有在整个存储单元区域(21)上延伸的部分或至少包括存储单元区域(21)中的板状电极(43)和位触点形成部分(24)的区域, 在外围电路区域(31)中形成接触形成部(34),在平板电极形成膜(53)上形成第二层绝缘膜(15),钻头接触孔(25)和接触孔 )分别通过平板电极形成膜(53)分别形成在位接触形成部分(24)和接触形成部分(31)中,钻头接触孔(25)和接触孔(36)的侧表面是 分别涂覆有绝缘膜(26,37)的导电插塞(16,17)形成在钻头接触孔(25)和接触孔(36)中,位线(18)形成在第二层绝缘膜 (15),以便连接到导电塞(16,17)。
    • 33. 发明授权
    • Semiconductor device manufacturing method and semiconductor device
    • 半导体器件制造方法和半导体器件
    • US08227317B2
    • 2012-07-24
    • US12629150
    • 2009-12-02
    • Hideaki Kuroda
    • Hideaki Kuroda
    • H01L21/336
    • H01L27/105H01L21/84H01L22/14H01L22/20H01L27/11H01L27/1104H01L27/1116H01L27/1203H01L29/78H01L29/7855
    • A semiconductor device manufacturing method includes the steps of: forming a transistor on a surface side of a silicon layer of a silicon-on-insulator substrate, the silicon-on-insulator substrate being formed by laminating a substrate, an insulating layer, and the silicon layer; forming a first insulating film covering the transistor and a wiring section including a part electrically connected to the transistor on the silicon-on-insulator substrate; measuring a threshold voltage of the transistor through the wiring section; forming a supporting substrate on a surface of the first insulating film with a second insulating film interposed between the supporting substrate and the first insulating film; removing at least a part of the substrate and the insulating layer on a back side of the silicon-on-insulator substrate; and adjusting the threshold voltage of the transistor on a basis of the measured threshold voltage.
    • 半导体器件制造方法包括以下步骤:在绝缘体上硅衬底的硅层的表面侧上形成晶体管,绝缘体上硅衬底通过层叠衬底,绝缘层和 硅层; 形成覆盖晶体管的第一绝缘膜和包括与绝缘体上硅基板上的晶体管电连接的部分的布线部分; 通过所述布线部分测量所述晶体管的阈值电压; 在所述第一绝缘膜的表面上形成支撑衬底,其中所述第二绝缘膜置于所述支撑衬底和所述第一绝缘膜之间; 在绝缘体上硅衬底的背面去除衬底和绝缘层的至少一部分; 以及基于测量的阈值电压来调整晶体管的阈值电压。
    • 37. 发明授权
    • Electroacoustic transducer
    • 电声换能器
    • US07586241B2
    • 2009-09-08
    • US12126022
    • 2008-05-23
    • Hideaki KurodaYoshihiro Sonoda
    • Hideaki KurodaYoshihiro Sonoda
    • H01L41/08
    • H04R17/10
    • An electroacoustic transducer having one end portion of a first piezoelectric element and one end portion of a second piezoelectric element fixed to a frame such that the first piezoelectric element and the second piezoelectric element are supported by the frame in an opening of the frame in the cantilever manner. A flexible thin film is bonded to the frame and the first and second piezoelectric elements so that it covers at least a gap between each of the piezoelectric elements and the frame. The other end portions of the piezoelectric elements are free end portions, and face each other with a gap therebetween.
    • 一种电声换能器,其具有第一压电元件的一个端部和固定到框架的第二压电元件的一个端部,使得第一压电元件和第二压电元件由框架支撑在悬臂中的框架的开口中 方式。 柔性薄膜结合到框架和第一和第二压电元件,使得它覆盖每个压电元件和框架之间的至少间隙。 压电元件的另一端部是自由端部,并且彼此面对地间隔开。
    • 40. 发明授权
    • One time programmable semiconductor nonvolatile memory device and method for production of same
    • 一次可编程半导体非易失性存储器件及其制造方法
    • US06800527B2
    • 2004-10-05
    • US10366564
    • 2003-02-14
    • Yoshiaki HagiwaraHideaki KurodaMichitaka KubotaAkira Nakagawara
    • Yoshiaki HagiwaraHideaki KurodaMichitaka KubotaAkira Nakagawara
    • H01L218236
    • G11C17/16G11C2213/33G11C2213/71G11C2213/77G11C2213/79H01L27/112H01L2224/48091H01L2225/06568H01L2924/13091H01L2924/00014H01L2924/00
    • A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an opening reaching the impurity region, and a second insulating film and a second semiconductor layer of a second conductivity type stacked in the opening.
    • 一种提高氧化硅膜的绝缘破坏的再现性和可靠性的能够降低制造成本的半导体非易失性存储器件及其制造方法,其中以矩阵形式布置的每个存储单元具有绝缘膜破损型 保险丝,其包括形成在半导体衬底上的第一导电类型的杂质区,形成在所述半导体衬底上的第一绝缘膜,同时覆盖所述杂质区;形成在所述第一绝缘膜中的开口以到达所述杂质区;以及第一绝缘膜 第一导电类型的半导体层,第二绝缘膜和第二导电类型的第二半导体层,其从杂质区侧连续地堆叠在开口中,或者具有包含第一导电性的杂质区的绝缘膜断裂型熔丝 键入具有SOI结构的第一半导体层,第一绝缘膜 在SOI层上,到达杂质区的开口,以及层叠在开口中的第二绝缘膜和第二导电类型的第二半导体层。