专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US5631671A Graphic pattern processing apparatus for processing pixels havings a number of bits which may be selected 失效
标题翻译：用于处理可以选择的具有多个位的像素的图形处理装置
公开(公告)号：US5631671A
公开(公告)日：1997-05-20
申请号：US104572
申请日：1993-08-11
申请人： Koyo Katsura , Hideo Maejima , Hisashi Kajiwara
发明人： Koyo Katsura , Hideo Maejima , Hisashi Kajiwara
IPC分类号： G06T1/20 , G06T1/60 , G06T11/20 , G06T17/00 , G09G5/02 , G09G5/20 , G09G5/36 , G09G5/39 , G09G5/393 , G09G5/395 , G09G5/399
CPC分类号： G09G5/395 , G06T1/20 , G06T1/60 , G06T11/203 , G06T17/00 , G09G5/024 , G09G5/20 , G09G5/363 , G09G5/39 , G09G5/393 , G09G5/399 , G09G2360/127 , G09G5/36
摘要： A graphic pattern processing apparatus for accessing a memory which stores words of graphic data. A plurality of pixels is stored in each word and each pixel has a plurality of bits. Each pixel of the word may be selected by a pixel address supplied by a graphic data processor. The graphic data processor performs processing on the selected pixel in accordance with instructions received from a data processor.
摘要翻译：一种用于访问存储图形数据的字的存储器的图形处理装置。在每个字中存储多个像素，并且每个像素具有多个位。字的每个像素可以由图形数据处理器提供的像素地址来选择。图形数据处理器根据从数据处理器接收的指令对所选择的像素执行处理。

32. 发明授权

US5448689A Graphic data processing system 失效
标题翻译：图形数据处理系统
公开(公告)号：US5448689A
公开(公告)日：1995-09-05
申请号：US234772
申请日：1994-04-28
申请人： Shigeru Matsuo , Koyo Katsura , Jun Sato , Takashi Sone , Masakatu Yokoyama
发明人： Shigeru Matsuo , Koyo Katsura , Jun Sato , Takashi Sone , Masakatu Yokoyama
IPC分类号： G06T17/00 , G06F15/62
CPC分类号： G06T17/00
摘要： A graphic processor which controls reading, writing and transfer of graphic data for a display memory that stores graphic data. The processor includes a first unit which stores first address information for addressing the display memory and first pixel address information which points a pixel position in a word specified by the first address information, a second unit which stores second address information for addressing the display memory and second pixel address information which points a pixel position in a word specified by the second address information, a third unit which shifts graphic data of multiple pixels included in two consecutive words to extract continuous 1-word graphic data, and a fourth unit which implements drawing computations pixel-wise concurrently for one word depending on the number of pixels included in a word. Even if transfer source graphic data lies across two consecutive words, the processor fetches the source data in single reading, processes the data word-wise at once, and stores the result in the display memory.
摘要翻译：用于控制用于存储图形数据的显示存储器的图形数据的读取，写入和传送的图形处理器。处理器包括第一单元，其存储用于寻址显示存储器的第一地址信息和指向由第一地址信息指定的字中的像素位置的第一像素地址信息;第二单元，存储用于寻址显示存储器的第二地址信息;以及指定由第二地址信息指定的字中的像素位置的第二像素地址信息;移动包括在两个连续字中的多个像素的图形数据以提取连续的1字图形数据的第三单元;以及实现图形的第四单元根据包含在一个单词中的像素数量，对一个单词进行像素同步的计算。即使传输源图形数据位于两个连续的字中，处理器以单次读取的方式读取源数据，一次处理数据，并将结果存储在显示存储器中。

33. 发明授权

US4615005A Data processing apparatus with clock signal control by microinstruction for reduced power consumption and method therefor 失效
标题翻译：具有通过微指令控制时钟信号的数据处理装置，用于降低功耗及其方法
公开(公告)号：US4615005A
公开(公告)日：1986-09-30
申请号：US632820
申请日：1984-07-20
申请人： Hideo Maejima , Koyo Katsura , Toshimasa Kihara , Yasushi Akao
发明人： Hideo Maejima , Koyo Katsura , Toshimasa Kihara , Yasushi Akao
IPC分类号： G06F1/04 , G06F1/32 , G06F9/30 , G06F11/00 , G06F7/38
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/324 , Y02B60/1217
摘要： Disclosed is a method of controlling the supply of a clock signal to a logic circuit, especially, a logic circuit composed of C-MOS gates for further reducing the power consumption. According to the control method, a clock signal supply inhibit instruction is stored, so that, when this instruction is read out, the supply of the clock signal to the logic circuit is inhibited, or its level is fixed at a specific signal level. In response to the application of an interrupt signal, the clock signal having been inhibited to be supplied to the logic circuit starts to be supplied to the logic circuit again. The circuit region or regions for which the supply of the clock signal is to be inhibited can be freely selected for the purpose of control. Thus, the method is especially effective when it is desired to closely control the saving of power consumed by the logic circuit.
摘要翻译：公开了一种控制向逻辑电路提供时钟信号的方法，特别是由用于进一步降低功耗的C-MOS门组成的逻辑电路。根据控制方法，存储时钟信号供给禁止指令，使得当读出该指令时，禁止向逻辑电路提供时钟信号，或者将其电平固定在特定信号电平。响应于中断信号的应用，被禁止提供给逻辑电路的时钟信号开始再次提供给逻辑电路。为了控制，可以自由地选择要禁止提供时钟信号的电路区域。因此，当期望密切控制逻辑电路消耗的功率的节省时，该方法特别有效。

34. 发明授权

US08332683B2 Data processing system and image processing system 失效
标题翻译：数据处理系统和图像处理系统
公开(公告)号：US08332683B2
公开(公告)日：2012-12-11
申请号：US12731442
申请日：2010-03-25
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1/04
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译：一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

35. 发明授权

US07711976B2 Data processing system and image processing system 失效
标题翻译：数据处理系统和图像处理系统
公开(公告)号：US07711976B2
公开(公告)日：2010-05-04
申请号：US11826136
申请日：2007-07-13
申请人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
发明人： Jun Satoh , Kazushige Yamagishi , Keisuke Nakashima , Koyo Katsura , Takashi Miyamoto , Mitsuru Watabe , Kenichiroh Ohmura
IPC分类号： G06F1/04
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
摘要翻译：一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

36. 发明申请

US20050041489A1 Data processing apparatus and shading apparatus 失效
标题翻译：数据处理装置和遮光装置
公开(公告)号：US20050041489A1
公开(公告)日：2005-02-24
申请号：US10947275
申请日：2004-09-23
申请人： Yasuhiro Nakatsuka , Shigeru Matsuo , Jun Satoh , Masanori Miyoshi , Koyo Katsura , Takashi Sone
发明人： Yasuhiro Nakatsuka , Shigeru Matsuo , Jun Satoh , Masanori Miyoshi , Koyo Katsura , Takashi Sone
IPC分类号： G06T15/50 , G06T15/80 , G11C7/00
CPC分类号： G06T1/60 , G06T11/40 , G06T15/50 , G06T15/80
摘要： In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.
摘要翻译：在数据处理器中使用的数据处理器和着色装置中，数据处理器根据存储器或翻译后备缓冲器的信息来选择一个地址。因此，即使在访问相同的数据的情况下，也可以根据硬件，被处理对象，处理等来采用高速的不同的地址。作为图像的顶点的参数，给出多个几何矢量，矢量被内插在图像中，并且使用通过内插生成的矢量来计算图中每个小区域的亮度。因此，即使当硬件的数量和图像的程度小时，也可以高精度和高速度地表现聚光灯或高光。

37. 发明授权

US06781590B2 Graphic processing system having bus connection control functions 失效
标题翻译：具有总线连接控制功能的图形处理系统
公开(公告)号：US06781590B2
公开(公告)日：2004-08-24
申请号：US09988157
申请日：2001-11-19
申请人： Koyo Katsura , Shigeru Matsuo , Jun Sato , Takashi Sone , Yoshikazu Yokota , Masahiko Kikuchi
发明人： Koyo Katsura , Shigeru Matsuo , Jun Sato , Takashi Sone , Yoshikazu Yokota , Masahiko Kikuchi
IPC分类号： G06F1300
CPC分类号： G06T11/203 , G06T1/20 , G09G5/024 , G09G5/393 , G09G5/399
摘要： A graphic processing system having a main memory for storing a program and information corresponding to pixels, a main processor for executing a program transferred from the main memory or from external to control the system, display/output devices for outputting graphic information attained by a control of pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels output to the display/output devices, and a graphic processor for receiving a command and parameter information from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure, and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or frame buffer.
摘要翻译：一种图形处理系统，具有用于存储程序的主存储器和对应于像素的信息，用于执行从主存储器传送或从外部传送的程序的主处理器来控制系统，用于输出通过控制获得的图形信息的显示/输出装置用于存储对应于输出到显示/输出设备的像素的信息的帧缓冲器，以及用于从主存储器和/或主处理器接收命令和参数信息的图形处理器，用于生成字符和图形数据，并且用于执行包括执行绘图处理的传送控制，以通过第一和第二地址总线以及第一和第二数据总线将生成的数据传送到主存储器和/或帧缓冲器。

38. 发明授权

US06492992B2 Graphic pattern processing apparatus 失效
标题翻译：图形处理装置
公开(公告)号：US06492992B2
公开(公告)日：2002-12-10
申请号：US09932895
申请日：2001-08-21
申请人： Koyo Katsura , Hideo Maejima , Hisashi Kajiwara
发明人： Koyo Katsura , Hideo Maejima , Hisashi Kajiwara
IPC分类号： G06F1210
CPC分类号： G09G5/395 , G06T1/20 , G06T1/60 , G06T11/203 , G06T17/00 , G09G5/024 , G09G5/20 , G09G5/36 , G09G5/363 , G09G5/39 , G09G5/393 , G09G5/399 , G09G2360/127
摘要： A data processing apparatus which processes data held in memory. The data processing apparatus includes an address operation unit which obtains an address to read one-word data from the memory, wherein the one-word data is a unit of data access to the memory, and a logical operation unit which determines a content of an operation on a field basis based on information which designates the number of bits per field to construct one-word data with a plurality of fields having a same number of bits. The logical operation unit, based on the content thus determined, performs the operation in parallel on the fields of the one-word data read from the memory by the address thus obtained.
摘要翻译：一种处理存储器中保存的数据的数据处理装置。该数据处理装置包括一个地址操作单元，该地址操作单元从存储器中获取一个单字数据的地址，其中该单字数据是对该存储器的一个数据访问单元，以及一个逻辑运算单元，基于指定每个字段的位数来构造具有相同位数的多个字段的一个字数据的信息的字段操作。基于这样确定的内容的逻辑运算单元，通过这样获得的地址，对从存储器读出的一字数据的字段并行地进行操作。

39. 发明授权

US06173253B2 Sentence processing apparatus and method thereof,utilizing dictionaries to interpolate elliptic characters or symbols 失效
标题翻译：句子处理装置及其方法，利用字典来内插椭圆字符或符号
公开(公告)号：US06173253B2
公开(公告)日：2001-01-09
申请号：US09275025
申请日：1999-03-24
申请人： Keiko Abe , Soshiro Kuzunuki , Koyo Katsura , Toshimi Yokota , Masaki Miura
发明人： Keiko Abe , Soshiro Kuzunuki , Koyo Katsura , Toshimi Yokota , Masaki Miura
IPC分类号： G06F1724
CPC分类号： G06F17/21 , G06F17/2795
摘要： A document or sentence processing apparatus having an input unit for inputting characters, a display unit for displaying input characters and a processing unit for converting and editing the input characters, in which the processing unit has a candidate word extraction unit which extracts candidates for the words with their characters omitted and/or omitted words themselves by referring to the vocabulary dictionary storing words and their usage frequency, to the dictionary of transition between words defining the information on the transition between words and the probability of the transition between words, and by searching the characters before and after the elliptic character included in the input sentence into the vocabulary dictionary, and a determination unit which selects a single word among the extracted candidate words by referring to the dictionary of transition between words.
摘要翻译：一种具有用于输入字符的输入单元的文档或句子处理装置，用于显示输入字符的显示单元和用于转换和编辑输入字符的处理单元，其中处理单元具有提取词语候选的候选词提取单元通过参考存储单词及其使用频率的词汇词典来省略和/或省略单词，并将其定义为词汇之间的转换信息和词汇之间的转换概率之间的转换词典，并通过搜索包括在输入语句中的椭圆字符之前和之后的字符到词汇词典中，以及确定单元，通过参考词之间的转换字典来选择提取的候选词中的单个单词。

40. 发明授权

US5751930A Graphic processing system 失效
标题翻译：图形处理系统
公开(公告)号：US5751930A
公开(公告)日：1998-05-12
申请号：US213820
申请日：1994-03-16
申请人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
发明人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
IPC分类号： G09G5/40 , G06F12/00 , G09G1/02 , G09G1/06 , G09G1/16 , G09G5/22 , G09G5/24 , G09G5/26 , G09G5/36 , G09G5/38 , G09G5/39 , G09G5/393 , G09G5/399 , G06T3/40 , G06T3/60
CPC分类号： G09G5/393 , G09G5/22 , G09G5/26 , G09G5/363
摘要： A graphic processing system for text display which includes a data processing unit, composed of a memory and a processing unit, for creating character code information, and a graphic data processing unit, composed of a graphic data processor and a frame buffer, for creating pixel information. The text display is performed by creating character code information in the data processing unit, supplying the character code information from the data processing unit to the graphic data processor, creating addresses on the frame buffer corresponding to the character code information by the graphic data processor, reading out a character font from a second area of the frame buffer using the created addresses, writing the read-out character font in a predetermined position of a first area of the frame buffer, and outputting the display data at the first area of the frame buffer to a display unit.
摘要翻译：一种用于文本显示的图形处理系统，包括由用于创建字符代码信息的存储器和处理单元组成的数据处理单元，以及由图形数据处理器和帧缓冲器组成的用于创建像素的图形数据处理单元信息。通过在数据处理单元中产生字符代码信息，从数据处理单元向图形数据处理器提供字符代码信息，通过图形数据处理器创建对应于字符代码信息的帧缓冲器上的地址来执行文本显示，使用所创建的地址从帧缓冲器的第二区域读出字符字体，将读出的字符字体写入帧缓冲器的第一区域的预定位置，并在帧的第一区域输出显示数据缓冲到显示单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式