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31. 发明申请

US20050098845A1 Semiconductor device with horizontal MOSFET and schottky barrier diode provided on single substrate 失效
标题翻译：在单个衬底上提供具有水平MOSFET和肖特基势垒二极管的半导体器件
公开(公告)号：US20050098845A1
公开(公告)日：2005-05-12
申请号：US10959201
申请日：2004-10-07
申请人： Tomoko Matsudai , Kazutoshi Nakamura , Akio Nakagawa
发明人： Tomoko Matsudai , Kazutoshi Nakamura , Akio Nakagawa
IPC分类号： H01L29/872 , H01L21/8234 , H01L27/06 , H01L27/07 , H01L29/47 , H01L29/76
CPC分类号： H01L27/0727
摘要： A MOS field-effect transistor includes a semiconductor substrate of a first-conductivity type, a semiconductor layer of the first-conductivity type, a source region of a second-conductivity type, a first drain region of the second-conductivity type, a resurf layer of the second-conductivity type provided in the surface of the semiconductor layer between the source region and the first drain region in contact with the first drain region, and having a lower impurity concentration than the first drain region, a gate insulation film, and a gate electrode provided on the gate insulation film between the source region and resurf layer. A Schottky barrier diode includes a second drain region of the second-conductivity type provided in the surface of the semiconductor layer separate from the first drain region in a direction away from the gate electrode, and a Schottky electrode provided on the semiconductor layer between the first and second drain regions.
摘要翻译： MOS场效应晶体管包括第一导电类型的半导体衬底，第一导电类型的半导体层，第二导电类型的源极区域，第二导电类型的第一漏极区域，第二导电类型的半导体层，所述第二导电型层设置在与所述第一漏极区域接触的所述源极区域和所述第一漏极区域之间的所述半导体层的表面中，并且具有比所述第一漏极区域低的杂质浓度，栅极绝缘膜和栅电极，设置在源极区域和复合层之间的栅极绝缘膜上。肖特基势垒二极管包括设置在半导体层的表面上的第二导电类型的第二漏极区域，该第二漏极区域在远离栅极电极的方向上与第一漏极区域分开，以及肖特基电极，设置在第一和第二漏区。

32. 发明授权

US06878992B2 Vertical-type power MOSFET with a gate formed in a trench 有权
标题翻译：垂直型功率MOSFET，其栅极形成在沟槽中
公开(公告)号：US06878992B2
公开(公告)日：2005-04-12
申请号：US10091423
申请日：2002-03-07
申请人： Yusuke Kawaguchi , Norio Yasuhara , Kazutoshi Nakamura , Akio Nakagawa , Syotaro Ono
发明人： Yusuke Kawaguchi , Norio Yasuhara , Kazutoshi Nakamura , Akio Nakagawa , Syotaro Ono
IPC分类号： H01L21/28 , H01L21/336 , H01L29/41 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66666 , H01L29/42368 , H01L29/7828
摘要： A power MOSFET comprises, between source and drain electrodes, a low resistive semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a high resistive epitaxial layer of the first conductivity type formed on the drift layer, trenches formed to extend from a surface of the epitaxial layer into the drift layer, gate electrodes buried in the trenches with gate insulating films interposed between the gate electrodes and walls of the trenches, low resistive source layers of the first conductivity type formed in a surface region of the epitaxial layer adjacent to the gate insulating films, and a base layer of a second conductivity type formed in the surface region of the epitaxial layer, wherein the epitaxial layer intervening between the trenches is depleted in a case where 0 volt is applied between the source electrode and the gate electrodes.
摘要翻译：功率MOSFET在源极和漏极之间包括第一导电类型的低电阻半导体衬底，形成在半导体衬底上的第一导电类型的漂移层，形成在漂移上的第一导电类型的高电阻外延层形成为从外延层的表面延伸到漂移层中的沟槽，埋入沟槽中的栅电极，栅极绝缘膜插入在栅电极和沟槽的壁之间，形成在第一导电类型的低电阻源层与栅极绝缘膜相邻的外延层的表面区域和形成在外延层的表面区域中的第二导电类型的基极层，其中在0伏特的情况下，介于沟槽之间的外延层被耗尽施加在源电极和栅电极之间。

33. 发明授权

US06614077B2 Semiconductor device improved in ESD reliability 有权
标题翻译：半导体器件提高了ESD可靠性
公开(公告)号：US06614077B2
公开(公告)日：2003-09-02
申请号：US09796427
申请日：2001-03-02
申请人： Kazutoshi Nakamura , Akio Nakagawa , Yusuke Kawaguchi
发明人： Kazutoshi Nakamura , Akio Nakagawa , Yusuke Kawaguchi
IPC分类号： H01L2362
CPC分类号： H01L29/7393 , H01L29/7394 , H01L29/749 , H01L2924/0002 , H01L2924/00
摘要： In an LDMOS, a p+-type anode layer is formed adjacent to an n+-type drain layer. The anode layer makes no contribution to an operation of the LDMOS at a rated voltage and generates holes at the time of ESD. The holes flow into the base layer through the active layer. Electrons flow from a source layer into the drain layer through the active layer. A parasitic thyristor of the LDMOS thus operates, with the result that a source-to-drain holding voltage can be lowered when a large current flows and the current distribution can be uniformed.
摘要翻译：在LDMOS中，与n +型漏极层相邻形成p +型阳极层。阳极层对额定电压下的LDMOS的操作没有贡献，并且在ESD时产生空穴。孔通过活性层流入基层。电子从源极层通过有源层流入漏极层。因此，LDMOS的寄生晶闸管因此工作，结果是当大电流流动并且电流分布可以均匀化时，源极到漏极保持电压可以降低。

34. 发明授权

US06563193B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06563193B1
公开(公告)日：2003-05-13
申请号：US09670548
申请日：2000-09-27
申请人： Yusuke Kawaguchi , Kazutoshi Nakamura , Tomoko Matsudai , Hirofumi Nagano , Akio Nakagawa
发明人： Yusuke Kawaguchi , Kazutoshi Nakamura , Tomoko Matsudai , Hirofumi Nagano , Akio Nakagawa
IPC分类号： H01L27082
CPC分类号： H01L29/7317 , H01L21/76286 , H01L21/763 , H01L29/735
摘要： A semiconductor device comprises a substrate the surface of which is formed of an insulation region, a high resistance active layer of a first conductivity type formed on the substrate, a first semiconductor region of the first conductivity type having an impurity concentration higher than that of the active layer and selectively formed on a surface of the active layer, an emitter region of the second conductivity type selectively formed on a surface of the semiconductor region, a collector region of the second conductivity type selectively formed on a surface of the active layer, and a base contact region of the first conductivity type selectively formed on a surface of the active layer in separation from the emitter region and the collector region, respectively. When an inversion layer is formed at an interface between the insulation region and the active layer due to the voltage of the substrate, the semiconductor region suppresses an emitter current flowing via the inversion layer thereby allowing the emitter current to flow on the surface side of the active layer.
摘要翻译：半导体器件包括其表面由绝缘区域形成的衬底，形成在衬底上的第一导电类型的高电阻有源层，第一导电类型的第一半导体区域的杂质浓度高于有源层，并且选择性地形成在有源层的表面上，选择性地形成在半导体区域的表面上的第二导电类型的发射极区域，选择性地形成在有源层的表面上的第二导电类型的集电极区域，以及分别在与发射极区域和集电极区域分离的有源层的表面上分别形成有第一导电类型的基极接触区域。当由于衬底的电压而在绝缘区域和有源层之间的界面处形成反型层时，半导体区域抑制通过反转层流动的发射极电流，从而允许发射极电流在活动层

35. 发明授权

US06297534B1 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US06297534B1
公开(公告)日：2001-10-02
申请号：US09413811
申请日：1999-10-07
申请人： Yusuke Kawaguchi , Kazutoshi Nakamura , Akio Nakagawa
发明人： Yusuke Kawaguchi , Kazutoshi Nakamura , Akio Nakagawa
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/1095 , H01L29/7824
摘要： A first conductivity type active layer having high resistance is provided on an insulation region. A second conductivity type base layer is selectively formed on a surface of the first conductivity type active layer. A first conductivity type source layer is selectively formed on a surface of the second conductivity type base layer. A first conductivity type drain layer is selectively formed on a surface of the first conductivity type active layer. A gate electrode is formed facing, through a gate insulating film, a surface region of the second conductivity type base layer between the first conductivity type source layer and the first conductivity type active layer. A plurality of first and second conductivity type semiconductor regions are formed between the second conductivity type base layer and the first conductivity type drain layer. Each of the second conductivity type semiconductor regions is arranged alternately with each of the first conductivity type semiconductor regions. A drain current flows from the first conductivity type source layer to the first conductivity type drain layer through the first conductivity type semiconductor regions. Bottom portions of the second conductivity type semiconductor regions are shallower than the interface between the first conductivity type active layer and the insulation region. According to the present invention, low ON resistance and high withstand voltage are realized at the same time.
摘要翻译：在绝缘区域上设置具有高电阻的第一导电型有源层。在第一导电型有源层的表面上选择性地形成第二导电型基极层。第一导电型源极层选择性地形成在第二导电型基极层的表面上。第一导电型漏极层选择性地形成在第一导电型有源层的表面上。栅极电极通过栅极绝缘膜形成在第一导电型源极层和第一导电型有源层之间的第二导电型基极层的表面区域。在第二导电型基极层和第一导电型漏极层之间形成多个第一和第二导电型半导体区域。每个第二导电类型半导体区域与第一导电类型半导体区域中的每一个交替布置。漏极电流通过第一导电型半导体区域从第一导电型源极层流到第一导电型漏极层。第二导电类型半导体区域的底部比第一导电型有源层和绝缘区域之间的界面浅。根据本发明，同时实现低导通电阻和高耐受电压。

36. 发明授权

US08730542B2 Sheet feeding device 有权
标题翻译：送纸装置
公开(公告)号：US08730542B2
公开(公告)日：2014-05-20
申请号：US13744491
申请日：2013-01-18
申请人： Kazutoshi Nakamura
发明人： Kazutoshi Nakamura
IPC分类号： H04N1/04
CPC分类号： B65H3/06 , B65H3/063 , B65H3/5223 , B65H2402/544 , B65H2601/5242
摘要： A sheet feeding device including a roller to apply conveying force to one of a plurality of stacked sheets, a separator piece to apply conveying resistance to the stacked sheets and to nip the one of the stacked sheets in cooperation with the roller, a movable member being movable with respect to the roller, a pair of spring arms configured to contact the stacked sheets at an upstream position along a conveying direction with respect to a nipping position between the roller and the separator piece, and a bridge to bridge between the pair of spring arms, is provided. The bridge and the movable member are slidably in contact with each other at least when the sheet feeding device is in a conveyable condition.
摘要翻译：一种送纸装置，包括：向多个堆叠纸张中的一个施加输送力的辊，分隔件，以对所述堆叠的纸张施加输送阻力，并与所述辊一起夹持所述堆叠的纸张中的一个;可动件，相对于辊可移动的一对弹簧臂，构造成在相对于辊和分离片之间的夹持位置的输送方向的上游位置处接触堆叠的片材的一对弹簧臂，以及在一对弹簧之间桥接的桥提供武器。至少当纸张馈送装置处于可传送状态时，桥和可移动部件可滑动地彼此接触。

37. 发明授权

US08466516B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08466516B2
公开(公告)日：2013-06-18
申请号：US12886461
申请日：2010-09-20
申请人： Kazutoshi Nakamura , Norio Yasuhara
发明人： Kazutoshi Nakamura , Norio Yasuhara
IPC分类号： H01L29/66
CPC分类号： H01L21/823857 , H01L21/823878 , H01L29/0619 , H01L29/1087 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, an element isolation insulator, a source layer of a second conductivity type, a drain layer of the second conductivity type, a contact layer of the first conductivity type and a gate electrode. The element isolation insulator is formed on the semiconductor substrate. The source layer is formed on the semiconductor substrate and is in contact with a side surface of the element isolation insulator. The drain layer is formed on the semiconductor substrate, is in contact with the side surface, and is spaced from the source layer. The contact layer is formed between the source layer and the drain layer. The gate electrode is provided on the element isolation insulator along the side surface.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的半导体衬底，元件隔离绝缘体，第二导电类型的源极层，第二导电类型的漏极层，第一导电类型的接触层和栅电极。元件隔离绝缘体形成在半导体衬底上。源极层形成在半导体衬底上并与元件隔离绝缘体的侧表面接触。漏极层形成在半导体基板上，与侧面接触，与源极层隔开。接触层形成在源极层和漏极层之间。栅电极沿着侧面设置在元件隔离绝缘体上。

38. 发明申请

US20110109295A1 SEMICONDUCTOR DEVICE AND DC-DC CONVERTER 审中-公开
标题翻译：半导体器件和DC-DC转换器
公开(公告)号：US20110109295A1
公开(公告)日：2011-05-12
申请号：US12886902
申请日：2010-09-21
申请人： Daisuke Minohara , Kazutoshi Nakamura
发明人： Daisuke Minohara , Kazutoshi Nakamura
IPC分类号： G05F3/08
CPC分类号： H02M1/088
摘要： According to one embodiment, a semiconductor device includes a first switching element and a second switching element. The first switching element has a first threshold voltage and a first gate electrode connected to a first gate wiring. The second switching element has a second threshold voltage and a second gate electrode connected to a second gate wiring. The second threshold voltage has a larger absolute value than the first threshold voltage. The second gate wiring has a larger resistance per unit length than the first gate wiring.
摘要翻译：根据一个实施例，半导体器件包括第一开关元件和第二开关元件。第一开关元件具有第一阈值电压和连接到第一栅极布线的第一栅电极。第二开关元件具有第二阈值电压和连接到第二栅极布线的第二栅电极。第二阈值电压具有比第一阈值电压更大的绝对值。第二栅极布线具有比第一栅极布线更大的每单位长度的电阻。

39. 发明授权

US07923807B2 Semiconductor device having an insulator including an inductive load driving circuit 失效
标题翻译：具有包括感性负载驱动电路的绝缘体的半导体装置
公开(公告)号：US07923807B2
公开(公告)日：2011-04-12
申请号：US11948289
申请日：2007-11-30
申请人： Kazutoshi Nakamura
发明人： Kazutoshi Nakamura
IPC分类号： H01L21/70
CPC分类号： H01L27/088 , H01L21/763 , H01L21/823481
摘要： A semiconductor device comprises a semiconductor substrate of the first conductivity type. A well layer of the first conductivity type is selectively formed on the semiconductor substrate. A first diffused layer of the second conductivity type is selectively formed on the well layer. A second diffused layer of the second conductivity type is formed on the well layer apart from the first diffused layer. A control electrode is formed on an insulating film between the first diffused layer and the second diffused layer. A main electrode is formed on each of the first diffused layer and the second diffused layer. A first trench is formed in the semiconductor substrate surrounding the well layer. A third diffused layer of the second conductivity type is formed contacting to the first trench. The second diffused layer and the third diffused layer are electrically kept at the same potential.
摘要翻译：半导体器件包括第一导电类型的半导体衬底。第一导电类型的阱层选择性地形成在半导体衬底上。第二导电类型的第一扩散层选择性地形成在阱层上。在与第一扩散层分开的阱层上形成第二导电类型的第二扩散层。在第一扩散层和第二扩散层之间的绝缘膜上形成控制电极。主电极形成在第一扩散层和第二扩散层中的每一个上。在围绕阱层的半导体衬底中形成第一沟槽。形成与第一沟槽接触的第二导电类型的第三扩散层。第二扩散层和第三扩散层电保持相同的电位。

40. 发明授权

US07863707B2 DC-DC converter 失效
标题翻译： DC-DC转换器
公开(公告)号：US07863707B2
公开(公告)日：2011-01-04
申请号：US12121171
申请日：2008-05-15
申请人： Kazutoshi Nakamura
发明人： Kazutoshi Nakamura
IPC分类号： H01L21/02
CPC分类号： H01L27/0921 , H01L21/823878 , H01L27/0629
摘要： A semiconductor device includes, in one semiconductor substrate: a plurality of switching elements connected between a terminal of an input voltage and an inductor; a driver circuit connected to a gate electrode of the switching element and driving the switching element; a reference voltage line connected to a source electrode of the switching element; a power supply line of the driver circuit; and a capacitor connected between the power supply line and the reference voltage line.
摘要翻译：一种半导体器件包括：在一个半导体衬底中：连接在输入电压的端子和电感器之间的多个开关元件; 连接到开关元件的栅电极并驱动开关元件的驱动电路; 连接到所述开关元件的源电极的参考电压线; 驱动电路的电源线; 以及连接在电源线和参考电压线之间的电容器。

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