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31. 发明授权

US07793238B1 Method and apparatus for improving a circuit layout using a hierarchical layout description 有权
标题翻译：使用层次布局描述改进电路布局的方法和装置
公开(公告)号：US07793238B1
公开(公告)日：2010-09-07
申请号：US12053874
申请日：2008-03-24
申请人： Peter Rabkin , Zhiyuan Wu , Min-Hsing Peter Chen , Jane W. Sowards , Michael J. Hart , Min-Fang Ho
发明人： Peter Rabkin , Zhiyuan Wu , Min-Hsing Peter Chen , Jane W. Sowards , Michael J. Hart , Min-Fang Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Various approaches for improving an integrated circuit layout. In one approach, a tree-type hierarchical layout representation of the circuit design is traversed. At each block visited during the traversing, a process determines whether there exists an improvement opportunity for each cell associated with the block. In response to determining that an improvement opportunity exists for a cell of a first block of the plurality of blocks, the process determines whether a modification to the cell satisfies one or more rules for every other block of the block type of the first block in the hierarchical representation. If the rules are satisfied, the modification is stored. Otherwise, the modification is discarded.
摘要翻译：用于改善集成电路布局的各种方法。在一种方法中，遍历了电路设计的树型分层布局表示。在遍历期间访问的每个块处，确定是否存在与该块相关联的每个单元的改进机会。响应于确定对于所述多个块的第一块的小区存在改进机会，所述过程确定对所述小区的修改是否满足所述小区的所述第一块的块类型的每个其他块的一个或多个规则分层表示。如果规则满足，则修改被存储。否则，修改被丢弃。

32. 发明授权

US07089527B2 Structures and methods for selectively applying a well bias to portions of a programmable device 有权
公开(公告)号：US07089527B2
公开(公告)日：2006-08-08
申请号：US10853982
申请日：2004-05-25
申请人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
发明人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
IPC分类号： G06F17/50
CPC分类号： H03K19/17792 , G06F17/5054 , H01L27/0928 , H01L27/11807
摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

33. 发明授权

US08886481B1 Reducing variation in multi-die integrated circuits 有权
标题翻译：减少多芯片集成电路的变化
公开(公告)号：US08886481B1
公开(公告)日：2014-11-11
申请号：US12835184
申请日：2010-07-13
申请人： Arifur Rahman , Michael J. Hart , Venkatesan Murali
发明人： Arifur Rahman , Michael J. Hart , Venkatesan Murali
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/14 , H01L2224/16225 , H01L2924/15311
摘要： A method of reducing variation in multi-die integrated circuits can include, for each of a plurality of dies, determining at least one performance metric and selecting at least two dies for inclusion within a multi-die integrated circuit according to the at least one performance metric. Systems and devices for executing the steps of the method are also described.
摘要翻译：减少多管芯集成电路中的变化的方法可以包括对于多个管芯中的每一个，确定至少一个性能度量并且根据至少一个性能选择至少两个管芯以包括在多管芯集成电路内度量。还描述了用于执行该方法的步骤的系统和设备。

34. 发明申请

US20110191729A1 Method and Apparatus for Interconnect Layout in an Integrated Circuit 有权
标题翻译：集成电路中互连布局的方法和装置
公开(公告)号：US20110191729A1
公开(公告)日：2011-08-04
申请号：US12696743
申请日：2010-01-29
申请人： Michael J. Hart
发明人： Michael J. Hart
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , H01L23/556 , H01L23/585 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/131 , H01L2924/0001 , H01L2924/01327 , H01L2924/14 , H01L2924/00 , H01L2924/014 , H01L2224/13099
摘要： An embodiment of the invention relates to a computer-implemented method of designing an integrated circuit (IC). In this embodiment, layout data describing conductive layers of the integrated circuit on a substrate is generated according to design specification data for the integrated circuit. The conductive layers include a topmost layer of bond pads. Metal structures in the layout data are modified to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each of the bond pads. A description of the layout data is generated on one or more masks for manufacturing the integrated circuit. By maximizing metal density in the superimposed plane, vertical channels through the dielectric material in the interconnect are reduced or eliminated. Thus, alpha particles cannot readily penetrate the interconnect and reach the underlying semiconductor substrate, reducing soft errors, such as single event upsets in memory cells.
摘要翻译：本发明的实施例涉及一种计算机实现的集成电路（IC）设计方法。在本实施例中，根据集成电路的设计规格数据生成描述基板上的集成电路的导电层的布局数据。导电层包括最上层的接合焊盘。修改布局数据中的金属结构以在每个接合焊盘下的阈值体积内使导电层的叠加平面中的金属密度最大化。在用于制造集成电路的一个或多个掩模上生成布局数据的描述。通过最大化叠加平面中的金属密度，通过互连中的电介质材料的垂直沟道被减少或消除。因此，α粒子不能容易地穿透互连并到达下面的半导体衬底，减少了软错误，例如存储器单元中的单事件混乱。

35. 发明授权

US06777978B2 Structures and methods for selectively applying a well bias to portions of a programmable device 有权
公开(公告)号：US06777978B2
公开(公告)日：2004-08-17
申请号：US10624617
申请日：2003-07-21
申请人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
发明人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
IPC分类号： H03K19173
CPC分类号： H03K19/17792 , G06F17/5054 , H01L27/0928 , H01L27/11807
摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

36. 发明授权

US5768179A Antifuse load sram cell 失效
标题翻译：消毒负载sram细胞
公开(公告)号：US5768179A
公开(公告)日：1998-06-16
申请号：US730541
申请日：1996-10-11
申请人： Michael J. Hart
发明人： Michael J. Hart
IPC分类号： G11C11/412 , G11C11/00
CPC分类号： G11C11/412
摘要： An antifuse functions as a resistive element in an SRAM cell. The antifuse layer, typically amorphous silicon, is formed to a thickness commensurate with the resistance required for proper functioning of the SRAM cell. The antifuse load SRAM cell of the present invention advantageously reduces chip area and simplifies the fabrication process. Specifically, the formation of the amorphous silicon layer is an easily controlled parameter which is therefore easily reproducible. Moreover, antifuse processing is compatible with standard CMOS processing.
摘要翻译：反熔丝用作SRAM单元中的电阻元件。反熔丝层（通常为非晶硅）形成为与SRAM单元正常工作所需的电阻相当的厚度。本发明的反熔断负载SRAM单元有利地减小了芯片面积并简化了制造工艺。具体地说，非晶硅层的形成是容易控制的参数，因此很容易重现。此外，反熔丝处理与标准CMOS处理兼容。

37. 发明授权

US5455790A High density EEPROM cell array which can selectively erase each byte of data in each row of the array 失效
标题翻译：高密度EEPROM单元阵列，可以选择性地擦除阵列每行数据的每个字节
公开(公告)号：US5455790A
公开(公告)日：1995-10-03
申请号：US243466
申请日：1994-05-16
申请人： Michael J. Hart , Albert M. Bergemont
发明人： Michael J. Hart , Albert M. Bergemont
IPC分类号： G11C16/10 , G11C16/14 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68
CPC分类号： G11C16/10 , G11C16/14 , H01L27/115 , H01L27/11521 , H01L29/7883 , Y10S438/972
摘要： Each byte of data in a high-density, electrically-erasable, programmable read-only-memory (EEPROM) cell array is selectively erased by forming a plurality of memory cells in each of a plurality of P-wells where the memory cells in each P-well are formed one byte wide by n rows in length. By forming the memory cells in each P-well to be one byte wide by n rows in length, each byte of data can be selectively erased by identifying the corresponding P-well and the row within the P-well.
摘要翻译：通过在多个P阱中的每个P阱中形成多个存储单元来选择性地擦除高密度，电可擦除可编程只读存储器（EEPROM）单元阵列中的每个字节的数据，其中每个P阱中的存储器单元 P-well形成一个字节宽，长度为n行。通过将每个P阱中的存储单元形成为一个字节宽，长度为n行，可以通过识别P阱中的相应P阱和行来选择性地擦除每个字节的数据。

38. 发明授权

US08692381B1 Integrated circuits with a resistance to single event upset occurrence and methods for providing the same 有权
标题翻译：具有抵抗单事件不稳定发生的集成电路和提供相同的方法
公开(公告)号：US08692381B1
公开(公告)日：2014-04-08
申请号：US12985918
申请日：2011-01-06
申请人： Michael J. Hart
发明人： Michael J. Hart
IPC分类号： H01L27/108
CPC分类号： H01L27/1104 , G11C11/4125 , H01L23/481 , H01L27/0207 , H01L28/90 , H01L29/66181 , H01L29/945 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods for reducing the Single Event Upset (SEU) susceptibility of a memory cell are disclosed. By using one or more Through Silicon Vias (TSVs) as capacitor(s) coupled to the Q and/or Qbar nodes of the memory cell, the critical charge (Qcrit) of the circuit is increased. In so doing, the memory cell has greater resistance to an SEU occurrence and reduced sensitivity to neutron and alpha or other charged particle events. The capacitor(s) can be coupled between the Q or Qbar node(s) and a silicon substrate, or between the Q and Qbar nodes, for example.
摘要翻译：公开了用于减小存储器单元的单事件触发（SEU）敏感性的集成电路和方法。通过使用一个或多个通硅通孔（TSV）作为耦合到存储器单元的Q和/或Qbar节点的电容器，电路的临界电荷（Qcrit）增加。在这样做时，存储单元对SEU发生具有更大的抵抗力，并降低对中子和α或其他带电粒子事件的敏感性。例如，电容器可以耦合在Q或Qbar节点与硅衬底之间，或Q和Qbar节点之间。

39. 发明授权

US08299564B1 Diffusion regions having different depths 有权
标题翻译：具有不同深度的扩散区域
公开(公告)号：US08299564B1
公开(公告)日：2012-10-30
申请号：US12559457
申请日：2009-09-14
申请人： Yun Wu , Bei Zhu , Zhiyuan Wu , Michael J. Hart
发明人： Yun Wu , Bei Zhu , Zhiyuan Wu , Michael J. Hart
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814
摘要： Formation of transistors, such as, e.g., PMOS transistors, with diffusion regions having different depths for equalization of performance among transistors of an integrated circuit is described. Shallow-trench isolation structures are formed in a substrate formed at least in part of silicon for providing the transistors with at least substantially equivalent channel widths and lengths. A series of masks and etches is performed to form first recesses and second recesses defined in the silicon having different depths and respectively associated with first and second transistors. The second recesses are deeper than the first recesses. A silicon germanium film is formed in the first recesses and the second recesses. The silicon germanium film in the second recesses is thicker than the silicon germanium film in the first recesses, in order to increase performance of the second transistor so it is closer to the performance of the first transistor.
摘要翻译：描述了具有扩散区域的诸如PMOS晶体管的晶体管的形成，其具有用于集成电路的晶体管之间的性能均衡的不同深度。浅沟槽隔离结构形成在至少部分硅中形成的衬底中，用于为晶体管提供至少基本相当的沟道宽度和长度。执行一系列掩模和蚀刻以形成在具有不同深度并且分别与第一和第二晶体管相关联的硅中限定的第一凹部和第二凹部。第二凹部比第一凹部更深。在第一凹部和第二凹部中形成硅锗膜。第二凹部中的硅锗膜比第一凹部中的硅锗膜厚，以便增加第二晶体管的性能，使得其更接近于第一晶体管的性能。

40. 发明申请

US20110210443A1 SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATION AND METHOD OF FORMING SAME 审中-公开
标题翻译：具有贝壳形状的下层金属化的半导体器件及其形成方法
公开(公告)号：US20110210443A1
公开(公告)日：2011-09-01
申请号：US12713855
申请日：2010-02-26
申请人： Michael J. Hart , Jan L. de Jong , Paul Y. Wu
发明人： Michael J. Hart , Jan L. de Jong , Paul Y. Wu
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L24/13 , H01L23/556 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05022 , H01L2224/05567 , H01L2224/1147 , H01L2224/11474 , H01L2224/1191 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/1355 , H01L2924/0002 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/36 , H01L2224/05552
摘要： An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at least a portion of a first metal layer; forming an under-bump metallization (UBM) layer over the tapered via and the first metal layer to form a UBM bucket; and forming a dielectric cap layer over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated.
摘要翻译：描述形成半导体器件的方法的实施例，该半导体器件包括在有源层上形成的具有有源层和互连的衬底。该方法包括：在互连上方形成具有暴露第一金属层的至少一部分的锥形通孔的电介质层; 在所述锥形通孔和所述第一金属层上形成凸起下金属化（UBM）层以形成UBM桶; 以及在介电层和UBM层的一部分上形成电介质盖层。 UBM桶被配置为支撑焊球，并且可以有利地阻挡具有相关入射角的焊球发射的所有α粒子到达IC的有源半导体区域。因此，减少或消除了诸如存储器单元中的单个事件的混乱的软错误。

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