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31. 发明申请

US20100151688A1 METHOD TO PREVENT THIN SPOT IN LARGE SIZE SYSTEM 审中-公开
标题翻译：在大型系统中防止漏点的方法
公开(公告)号：US20100151688A1
公开(公告)日：2010-06-17
申请号：US12634921
申请日：2009-12-10
申请人： Young Jin Choi , Gaku Furuta , Soo Young Choi , Beom Soo Park
发明人： Young Jin Choi , Gaku Furuta , Soo Young Choi , Beom Soo Park
IPC分类号： H01L21/3065 , H01L21/302
CPC分类号： C23C16/4583 , C23C16/505 , H01J37/32091 , H01J37/32733 , H01L21/68742
摘要： Embodiments disclosed herein generally include methods of ensuring uniform deposition on a substrate. The smallest gap between a portion of the substrate and the substrate support upon which the substrate rests may lead to uneven deposition of material or ‘thin spots’ on the substrate. Large area substrates, due to their size, are susceptible to numerous gaps at random locations. By inducing an electrostatic charge on the substrate prior to placing the substrate onto the substrate support, the substrate may be placed generally flush against the substrate support. The electrostatic charge on the substrate creates an attraction between the substrate and substrate support to pull substantially the entire surface of the substrate into contact with the substrate support. Material may then be substantially uniformly deposited on the substrate while reducing ‘thin spots’.
摘要翻译：本文公开的实施例通常包括确保在基底上均匀沉积的方法。衬底的一部分和衬底支撑物之间的最小间隙可能导致材料的不均匀沉积或衬底上的“薄点”。由于其大尺寸，大面积基板在随机位置易受许多间隙的影响。通过在将衬底放置在衬底支撑件上之前在衬底上引起静电电荷，衬底可以放置在与衬底支撑件相对齐齐的位置。衬底上的静电电荷在衬底和衬底支撑件之间产生吸引力，以基本上将衬底的整个表面拉到与衬底支撑件接触。然后可以将材料基本均匀地沉积在衬底上，同时减少“薄点”。

32. 发明申请

US20060019031A1 Deposition repeatability of PECVD films 有权
标题翻译： PECVD膜的沉积重复性
公开(公告)号：US20060019031A1
公开(公告)日：2006-01-26
申请号：US10898472
申请日：2004-07-23
申请人： Gaku Furuta , Tae Won , John White
发明人： Gaku Furuta , Tae Won , John White
IPC分类号： C23C16/00
CPC分类号： C23C16/0209 , C23C16/5096
摘要： We have a method of improving the deposition rate uniformity of the chemical vapor deposition (CVD) of films when a number of substrates are processed in series, sequentially in a deposition chamber. The method includes the plasma pre-heating of at least one processing volume structure within the processing volume which surrounds the substrate when the substrate is present in the deposition chamber. We also have a device-controlled method which adjusts the deposition time for a few substrates at the beginning of the processing of a number of substrates in series, sequentially in a deposition chamber, so that the deposited film thickness remains essentially constant during processing of the series of substrates. A combination of these methods into a single method provides the best overall results in terms of controlling average film thickness from substrate to substrate.
摘要翻译：当在沉积室中顺序地处理多个基板时，我们具有提高膜的化学气相沉积（CVD）的沉积速率均匀性的方法。该方法包括当衬底存在于沉积室中时，围绕衬底的处理体积内的至少一个处理体积结构的等离子体预热。我们还有一种装置控制的方法，其可以在沉积室中顺次地串联处理多个基板的开始时调整几个基板的沉积时间，使得沉积膜厚度在处理期间保持基本恒定系列底物。将这些方法组合成单一方法提供了从基材到底物控制平均膜厚度方面的最佳总体结果。

33. 发明授权

US08877301B2 Plasma processing including asymmetrically grounding a susceptor 有权
标题翻译：等离子体处理包括不对称接地的感受器
公开(公告)号：US08877301B2
公开(公告)日：2014-11-04
申请号：US13153641
申请日：2011-06-06
申请人： Gaku Furuta , Soo Young Choi , Young-Jin Choi
发明人： Gaku Furuta , Soo Young Choi , Young-Jin Choi
IPC分类号： C23C16/509 , C23C16/458 , C23C16/455 , H01J37/32
CPC分类号： C23C16/4585 , C23C16/45565 , C23C16/5096 , H01J37/32091 , H01J37/32568 , H01J37/32577 , H01J37/32623 , H01J37/32697
摘要： An asymmetrically grounded susceptor used in a plasma processing chamber for chemical vapor deposition onto large rectangular panels supported on and grounded by the susceptor. A plurality of grounding straps are connected between the periphery of the susceptor to the grounded vacuum chamber to shorten the grounding paths for RF electrons. Flexible straps allow the susceptor to vertically move. The straps provide a conductance to ground which is asymmetric around the periphery. The straps may be evenly spaced but have different thicknesses or different shapes or be removed from available grounding point and hence provide different RF conductances. The asymmetry is selected to improve the deposition uniformity and other qualities of the PECVD deposited film.
摘要翻译：用于等离子体处理室中的不对称接地的基座，用于化学气相沉积到由基座支撑并接地的大矩形面板上。多个接地带连接在基座的外围与接地的真空室之间，以缩短RF电子的接地路径。柔性带允许基座垂直移动。带子提供对周边不对称的地面电导。带可以是均匀间隔的，但是具有不同的厚度或不同的形状，或者从可用的接地点去除并因此提供不同的RF电导。选择不对称性以改善PECVD沉积膜的沉积均匀性和其他质量。

34. 发明授权

US08281739B2 RF shutter 有权
标题翻译：射频快门
公开(公告)号：US08281739B2
公开(公告)日：2012-10-09
申请号：US12040298
申请日：2008-02-29
申请人： Robin L. Tiner , Gaku Furuta , Yukinobu Adachi
发明人： Robin L. Tiner , Gaku Furuta , Yukinobu Adachi
IPC分类号： C23C16/00 , H01L21/00
CPC分类号： H01J37/32082 , H01J37/32623 , H01J37/32651 , H01J2237/0206
摘要： The present invention generally comprises an RF shutter assembly for use in a plasma processing apparatus. The RF shutter assembly may reduce the amount of plasma creep below the substrate and shadow frame during processing, thereby reducing the amount of deposition that occurs on undesired surfaces. By reducing the amount of deposition on undesired surfaces, particle flaking and thus, substrate contamination may be reduced.
摘要翻译：本发明通常包括用于等离子体处理装置的RF快门组件。 RF快门组件可以在处理期间减少基板和阴影框架下方的等离子体蠕变的量，从而减少在不期望的表面上发生的沉积量。通过减少不期望的表面上的沉积量，可能会降低颗粒剥落，从而可能降低底物污染。

35. 发明申请

US20120040536A1 A-SI SEASONING EFFECT TO IMPROVE SIN RUN-TO-RUN UNIFORMITY 有权
标题翻译： A-SI季节效应提高了单机运行的均匀性
公开(公告)号：US20120040536A1
公开(公告)日：2012-02-16
申请号：US13207315
申请日：2011-08-10
申请人： Gaku Furuta , Soo Young Choi , Beom Soo Park , Young-jin Choi , Omori Kenji
发明人： Gaku Furuta , Soo Young Choi , Beom Soo Park , Young-jin Choi , Omori Kenji
IPC分类号： H01L21/318
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/4404 , H01L21/02274 , H01L21/02299
摘要： Embodiments of the present invention provide methods for depositing a nitrogen-containing material on large-sized substrates disposed in a processing chamber. In one embodiment, a method includes processing a batch of substrates within a processing chamber to deposit a nitrogen-containing material on a substrate from the batch of substrates, and performing a seasoning process at predetermined intervals during processing the batch of substrates to deposit a conductive seasoning layer over a surface of a chamber component disposed in the processing chamber. The chamber component may include a gas distribution plate fabricated from a bare aluminum without anodizing. In one example, the conductive seasoning layer may include amorphous silicon, doped amorphous silicon, doped silicon, doped polysilicon, doped silicon carbide, or the like.
摘要翻译：本发明的实施方案提供了在设置在处理室中的大尺寸基板上沉积含氮材料的方法。在一个实施方案中，一种方法包括处理处理室内的一批衬底，以将一批含有底物的含氮材料从该批衬底上沉积，并在处理该批衬底期间以预定间隔进行调味过程以沉积导电在处理室中设置的腔室部件的表面上的调味层。腔室部件可以包括由裸铝制成而不阳极氧化的气体分配板。在一个示例中，导电调味层可以包括非晶硅，掺杂非晶硅，掺杂硅，掺杂多晶硅，掺杂碳化硅等。

36. 发明申请

US20110269274A1 THIN FILM TRANSISTORS HAVING MULTIPLE DOPED SILICON LAYERS 有权
标题翻译：具有多层掺杂硅层的薄膜晶体管
公开(公告)号：US20110269274A1
公开(公告)日：2011-11-03
申请号：US12913846
申请日：2010-10-28
申请人： Gaku Furuta , Soo Young Choi , Omori Kenji
发明人： Gaku Furuta , Soo Young Choi , Omori Kenji
IPC分类号： H01L21/336
CPC分类号： H01L29/66765 , G02F1/1362 , H01L29/78618
摘要： Embodiments of the present invention generally relate to a TFT and a method for its fabrication. The TFT disclosed herein is a silicon based TFT in which the active channel comprises amorphous silicon. Over the amorphous silicon, multiple layers of doped silicon are deposited in which the resistivity of the doped silicon layers is higher at the interface with the amorphous silicon layer as compared to the interface with the source and drain electrodes. Alternatively, a single doped silicon layer is deposited over the amorphous silicon in which the properties of the single doped layer change throughout the thickness. It is better to have a lower resistivity at the interface with the source and drain electrodes, but lower resistivity usually means less substrate throughput. By utilizing multiple or graded layers, low resistivity can be achieved. The embodiments disclosed herein include low resistivity without sacrificing substrate throughput.
摘要翻译：本发明的实施例一般涉及TFT及其制造方法。本文公开的TFT是其中有源沟道包括非晶硅的硅基TFT。在非晶硅上，沉积了多层掺杂硅，其中掺杂硅层的电阻率在与非晶硅层的界面处比与源极和漏极的界面相比更高。或者，在非晶硅上沉积单个掺杂的硅层，其中单个掺杂层的性质在整个厚度上变化。在与源极和漏极的界面处具有较低的电阻率是更好的，但较低的电阻率通常意味着较少的衬底生产量。通过利用多层或分层，可以实现低电阻率。本文公开的实施例包括低电阻率而不牺牲基板生产量。

37. 发明授权

US07988875B2 Differential etch rate control of layers deposited by chemical vapor deposition 有权
标题翻译：通过化学气相沉积沉积的层的差分蚀刻速率控制
公开(公告)号：US07988875B2
公开(公告)日：2011-08-02
申请号：US12027964
申请日：2008-02-07
申请人： Soo Young Choi , Gaku Furuta
发明人： Soo Young Choi , Gaku Furuta
IPC分类号： C23F3/00
CPC分类号： H01L21/31116 , C03C17/34 , C03C2218/33 , C23C16/308 , C23C16/345 , C23C16/401 , H01L21/31111
摘要： A method and apparatus is provided for controlling the etch profile of a multilayer layer stack by depositing a first and second material layer with differential etch rates in the same or different processing chamber. In one embodiment of the invention, a process for etching substrate material is provided including depositing a first silicon-containing material layer having a first etch rate on the substrate surface from a nitrogen-containing precursor at a first flow rate and a silicon-containing precursor, depositing a second silicon-containing material layer having a second etch rate different than the first etch rate on the first silicon-containing material layer from the nitrogen-containing precursor at a second flow rate different than the first flow rate and the silicon-containing precursor, etching the first silicon-containing material layer and the second silicon-containing material layer, and forming a taper etch profile in the first silicon-containing material layer and the second silicon-containing material layer.
摘要翻译：提供了一种方法和装置，用于通过在相同或不同的处理室中沉积差分蚀刻速率的第一和第二材料层来控制多层堆叠的蚀刻轮廓。在本发明的一个实施例中，提供了一种用于蚀刻衬底材料的方法，包括：以第一流速从含氮前体沉积具有第一蚀刻速率的第一含硅材料层，并在第一流速下沉积含硅前体在第一含硅材料层上以不同于第一流速的第二流量从含氮前体沉积具有与第一蚀刻速率不同的第二蚀刻速率的第二含硅材料层，蚀刻第一含硅材料层和第二含硅材料层，并在第一含硅材料层和第二含硅材料层中形成锥形蚀刻轮廓。

38. 发明授权

US08299466B2 Thin film transistors having multiple doped silicon layers 有权
标题翻译：具有多个掺杂硅层的薄膜晶体管
公开(公告)号：US08299466B2
公开(公告)日：2012-10-30
申请号：US12913846
申请日：2010-10-28
申请人： Gaku Furuta , Soo Young Choi , Omori Kenji
发明人： Gaku Furuta , Soo Young Choi , Omori Kenji
IPC分类号： H01L31/00
CPC分类号： H01L29/66765 , G02F1/1362 , H01L29/78618
摘要： Embodiments of the present invention generally relate to a TFT and a method for its fabrication. The TFT disclosed herein is a silicon based TFT in which the active channel comprises amorphous silicon. Over the amorphous silicon, multiple layers of doped silicon are deposited in which the resistivity of the doped silicon layers is higher at the interface with the amorphous silicon layer as compared to the interface with the source and drain electrodes. Alternatively, a single doped silicon layer is deposited over the amorphous silicon in which the properties of the single doped layer change throughout the thickness. It is better to have a lower resistivity at the interface with the source and drain electrodes, but lower resistivity usually means less substrate throughput. By utilizing multiple or graded layers, low resistivity can be achieved. The embodiments disclosed herein include low resistivity without sacrificing substrate throughput.
摘要翻译：本发明的实施例一般涉及TFT及其制造方法。本文公开的TFT是其中有源沟道包括非晶硅的硅基TFT。在非晶硅上，沉积了多层掺杂的硅，其中掺杂硅层的电阻率在与非晶硅层的界面处比与源极和漏极的界面相比更高。或者，在非晶硅上沉积单个掺杂的硅层，其中单个掺杂层的性质在整个厚度上变化。在与源极和漏极的界面处具有较低的电阻率是更好的，但较低的电阻率通常意味着较少的衬底生产量。通过利用多层或分层，可以实现低电阻率。本文公开的实施例包括低电阻率而不牺牲基板生产量。

39. 发明授权

US07972470B2 Asymmetric grounding of rectangular susceptor 有权
标题翻译：矩形基座不对称接地
公开(公告)号：US07972470B2
公开(公告)日：2011-07-05
申请号：US11775359
申请日：2007-07-10
申请人： Gaku Furuta , Soo Young Choi , Young-Jin Choi
发明人： Gaku Furuta , Soo Young Choi , Young-Jin Choi
IPC分类号： H01L21/306 , C23C16/00
CPC分类号： C23C16/4585 , C23C16/45565 , C23C16/5096 , H01J37/32091 , H01J37/32568 , H01J37/32577 , H01J37/32623 , H01J37/32697
摘要： An asymmetrically grounded susceptor used in a plasma processing chamber for chemical vapor deposition onto large rectangular panels supported on and grounded by the susceptor. A plurality of grounding straps are connected between the periphery of the susceptor to the grounded vacuum chamber to shorten the grounding paths for RF electrons. Flexible straps allow the susceptor to vertically move. The straps provide a conductance to ground which is asymmetric around the periphery. The straps may be evenly spaced but have different thicknesses or different shapes or be removed from available grounding point and hence provide different RF conductances. The asymmetry is selected to improve the deposition uniformity and other qualities of the PECVD deposited film.
摘要翻译：用于等离子体处理室中的不对称接地的基座，用于化学气相沉积到由基座支撑并接地的大矩形面板上。多个接地带连接在基座的外围与接地的真空室之间，以缩短RF电子的接地路径。柔性带允许基座垂直移动。带子提供对周边不对称的地面电导。带可以是均匀间隔的，但是具有不同的厚度或不同的形状，或者从可用的接地点去除并因此提供不同的RF电导。选择不对称性以改善PECVD沉积膜的沉积均匀性和其他质量。

40. 发明申请

US20050233595A1 Controlling the properties and uniformity of a silicon nitride film by controlling the film forming precursors 有权
标题翻译：通过控制成膜前体来控制氮化硅膜的性能和均匀性
公开(公告)号：US20050233595A1
公开(公告)日：2005-10-20
申请号：US10829016
申请日：2004-04-20
申请人： Soo Choi , Tae Won , Gaku Furuta , Qunhua Wang , John White , Beom Park
发明人： Soo Choi , Tae Won , Gaku Furuta , Qunhua Wang , John White , Beom Park
IPC分类号： C23C16/34 , H01L21/318 , H01L21/336 , H01L21/469 , H01L29/49 , H01L29/786
CPC分类号： H01L21/0217 , C23C16/345 , H01L21/02274 , H01L21/3185 , H01L29/4908 , H01L29/66765 , H01L29/78669
摘要： We have developed a method of PECVD depositing a-SiNx:H films which are useful in a TFT device as gate dielectric and passivation layers, when a series of TFT devices are arrayed over a substrate having a surface area larger than about 1 m2, which may be in the range of about 4.1 m2, and even as large as 9 m2. The a-SiNx:H films provide a uniformity of film thickness and uniformity of film properties, including chemical composition, which are necessary over such large substrate surface areas. The films produced by the method are useful for both liquid crystal active matrix displays and for organic light emitting diode control.
摘要翻译：我们已经开发了一种PECVD沉积a-SiN＆lt; x＆gt;：H膜的方法，其可用于TFT器件作为栅极电介质和钝化层，当一系列TFT器件排列在具有表面的衬底上时大于约1m 2的区域，其可以在约4.1m 2范围内，甚至大至9m 2/2。 a-SiN＆lt; x＆gt;：H膜提供了膜厚度的均匀性和膜特性的均匀性，包括在这种大的基材表面区域上必需的化学成分。通过该方法生产的膜对于液晶有源矩阵显示器和有机发光二极管控制是有用的。

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