专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20090294837A1 Nonvolatile Memory Devices Having a Fin Shaped Active Region 失效
标题翻译：具有鳍形活动区域的非易失性存储器件
公开(公告)号：US20090294837A1
公开(公告)日：2009-12-03
申请号：US12536740
申请日：2009-08-06
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/792 , H01L29/78
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.
摘要翻译：非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。翅片形有源区形成在器件隔离层的各部分之间。侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。侧壁保护层可以使用器件隔离层形成。或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

32. 发明授权

US07480178B2 NAND flash memory device having dummy memory cells and methods of operating same 有权
标题翻译：具有虚拟存储单元的NAND闪存器件及其操作方法
公开(公告)号：US07480178B2
公开(公告)日：2009-01-20
申请号：US11279607
申请日：2006-04-13
申请人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
发明人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

33. 发明授权

US07397093B2 Semiconductor devices with sidewall conductive patterns methods of fabricating the same 有权
标题翻译：具有侧壁导电图案的半导体器件制造方法
公开(公告)号：US07397093B2
公开(公告)日：2008-07-08
申请号：US11241458
申请日：2005-09-30
申请人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
发明人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11529
摘要： A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.
摘要翻译：公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。下导电图案在基板上。绝缘图案位于下导电图案上。上导电图案位于与下导电图案相对的绝缘图案上。侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。侧壁导电图形电连接上导电图案和下导电图案。下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

34. 发明申请

US20080006872A1 Charge-trap nonvolatile memory devices and methods of fabricating the same 有权
标题翻译：电荷陷阱非易失性存储器件及其制造方法
公开(公告)号：US20080006872A1
公开(公告)日：2008-01-10
申请号：US11700315
申请日：2007-01-31
申请人： Chang-Seok Kang , Jung-Dal Choi , Ju-Hyung Kim , Jong-Sun Sel , Jae-Sung Sim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Jung-Dal Choi , Ju-Hyung Kim , Jong-Sun Sel , Jae-Sung Sim , Sang-Hun Jeon
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/115
摘要： Nonvolatile memory devices including device isolation patterns on a semiconductor substrate are provided. The device isolation patterns define a cell active region and a peripheral active region of the semiconductor substrate. Cell gate electrodes are provided that cross over the cell active regions. Memory cell patterns are provided between the cell gate electrodes and the cell active regions and extend toward the device isolation patterns. A tunnel insulation film is provided between the memory cell pattern and the cell active region. Related methods of fabricating nonvolatile memory devices are also provided herein.
摘要翻译：提供包括半导体衬底上的器件隔离图案的非易失性存储器件。器件隔离图案限定半导体衬底的单元有源区和外围有源区。提供跨越电池有源区的电池栅电极。在单元栅极电极和单元有源区之间提供存储单元图案，并朝向器件隔离图案延伸。在存储单元图形和单元有源区之间设置隧道绝缘膜。本文还提供了制造非易失性存储器件的相关方法。

35. 发明申请

US20060234447A1 Methods of fabricating nonvolatile memory devices and related devices 失效
标题翻译：制造非易失性存储器件和相关器件的方法
公开(公告)号：US20060234447A1
公开(公告)日：2006-10-19
申请号：US11403964
申请日：2006-04-13
申请人： Jung-Dal Choi , Yun-Seung Shin , Jong-Sun Sel
发明人： Jung-Dal Choi , Yun-Seung Shin , Jong-Sun Sel
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11531
摘要： Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.
摘要翻译：提供制造非易失性存储器件的方法。在基板上形成隔离层。衬底具有存储区和阱接触区，并且隔离层限定衬底的有源区。在有源区上形成栅极绝缘层。栅极绝缘层被图案化以在其中限定开口。开口暴露衬底的阱接触区域的至少一部分，并且充当用于隔离层的后续蚀刻期间产生的电荷的电荷路径。还提供了相关的存储器件。

36. 发明授权

US08329574B2 Methods of fabricating flash memory devices having shared sub active regions 有权
标题翻译：制造具有共享子有源区的闪存器件的方法
公开(公告)号：US08329574B2
公开(公告)日：2012-12-11
申请号：US13230978
申请日：2011-09-13
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/44
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , Y10S257/905
摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
摘要翻译：闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

37. 发明授权

US07884425B2 Non-volatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US07884425B2
公开(公告)日：2011-02-08
申请号：US12257939
申请日：2008-10-24
申请人： Jong-Sun Sel , Jung-Dal Choi , Choong-Ho Lee , Ju-Hyuck Chung , Hee-Soo Kang , Dong-uk Choi
发明人： Jong-Sun Sel , Jung-Dal Choi , Choong-Ho Lee , Ju-Hyuck Chung , Hee-Soo Kang , Dong-uk Choi
IPC分类号： H01L21/70
CPC分类号： H01L23/485 , H01L21/76804 , H01L21/76816 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a semiconductor memory device includes a substrate having first and second active regions. The first active region includes a first source and drain regions and the second active region includes a second source and drain regions. A first interlayer dielectric is located over the substrate. A first conductive structure extends through the first interlayer dielectric. A first bit line is on the first interlayer dielectric. A second interlayer dielectric is on the first interlayer dielectric. A contact hole extends through the second and first interlayer dielectrics. The device includes a second conductive structure within the contact hole and extending through the first and second interlayer dielectrics. A second bit line is on the second interlayer dielectric. A width of the contact hole at a bottom of the second interlayer dielectric is less than or substantially equal to a width at a top of the second interlayer dielectric.
摘要翻译：在一个实施例中，半导体存储器件包括具有第一和第二有源区的衬底。第一有源区包括第一源区和漏区，第二有源区包括第二源区和漏区。第一层间电介质位于衬底上。第一导电结构延伸穿过第一层间电介质。第一位线位于第一层间电介质上。第二层间电介质在第一层间电介质上。接触孔延伸穿过第二和第一层间电介质。该装置包括接触孔内的第二导电结构并且延伸穿过第一和第二层间电介质。第二位线位于第二层间电介质上。第二层间电介质的底部处的接触孔的宽度小于或基本上等于第二层间电介质顶部的宽度。

38. 发明授权

US07881114B2 NAND flash memory device having dummy memory cells and methods of operating same 有权
标题翻译：具有虚拟存储单元的NAND闪存器件及其操作方法
公开(公告)号：US07881114B2
公开(公告)日：2011-02-01
申请号：US12340250
申请日：2008-12-19
申请人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
发明人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

39. 发明授权

US07723776B2 Flash memory devices having shared sub active regions 有权
标题翻译：具有共享子活动区域的闪存设备
公开(公告)号：US07723776B2
公开(公告)日：2010-05-25
申请号：US11376371
申请日：2006-03-15
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , Y10S257/905
摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
摘要翻译：闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

40. 发明申请

US20080246073A1 Nonvolatile Memory Devices Including a Resistor Region 审中-公开
标题翻译：包括电阻器区域的非易失性存储器件
公开(公告)号：US20080246073A1
公开(公告)日：2008-10-09
申请号：US12138712
申请日：2008-06-13
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/00
CPC分类号： H01L27/105 , B82Y10/00 , H01L21/823462 , H01L27/0629 , H01L27/11526 , H01L27/11546 , H01L27/11568
摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.
摘要翻译：形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。在电阻器区域中的器件隔离层上形成第一导电层。半导体衬底暴露在电池阵列区域中。电池绝缘层形成在包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的半导体衬底的一部分上。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式