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31. 发明授权

US07435619B2 Method of fabricating a 3-D package stacking system 有权
标题翻译：制造3-D封装堆叠系统的方法
公开(公告)号：US07435619B2
公开(公告)日：2008-10-14
申请号：US11307615
申请日：2006-02-14
申请人： Il Kwon Shim , Byung Joon Han , Seng Guan Chow
发明人： Il Kwon Shim , Byung Joon Han , Seng Guan Chow
IPC分类号： H01L21/00 , H01L23/02 , H05K7/00
CPC分类号： H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/105 , H01L25/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a system for 3D package stacking system, comprising providing a substrate, attaching a ball grid array package, in an inverted position, to the substrate, forming a lower package, the lower package having the ball grid array package and the substrate encapsulated by a molding compound and attaching a second integrated circuit package over the lower package.
摘要翻译：本发明提供了一种用于3D封装堆叠系统的系统，包括提供衬底，将反向位置的球栅阵列封装连接到衬底，形成下封装，下封装具有球栅阵列封装和衬底通过模制化合物封装并且将下一个封装上的第二集成电路封装。

32. 发明授权

US06642610B2 Wire bonding method and semiconductor package manufactured using the same 有权
公开(公告)号：US06642610B2
公开(公告)日：2003-11-04
申请号：US09745265
申请日：2000-12-20
申请人： Young Kuk Park , Byung Joon Han , Jae Dong Kim
发明人： Young Kuk Park , Byung Joon Han , Jae Dong Kim
IPC分类号： H01L2302
CPC分类号： H01L24/85 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L25/0655 , H01L25/0657 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/4847 , H01L2224/48479 , H01L2224/4848 , H01L2224/49113 , H01L2224/73265 , H01L2224/78301 , H01L2224/85051 , H01L2224/85181 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2224/4554
摘要： A semiconductor package including plural semiconductor chips, and a wire bonding step for electrically interconnecting the semiconductor chips, are disclosed. In an exemplary method, a substrate is provided. Conductive circuit patterns are provided outside of a chip mounting region of the substrate, and conductive transfer patterns are provided proximate to the chip mounting region. Chips are placed in the chip mounting region. Conductive wires are bonded between input/output pads of a first chip and respective transfer patterns, and other conductive wires are bonded between input/output pads of a second chip and the same transfer patterns, thereby electrically connecting respective input/output pads of the two chips through a pair of bond wires and an intermediate transfer pattern.

33. 发明授权

US06414396B1 Package for stacked integrated circuits 有权
标题翻译：堆叠集成电路封装
公开(公告)号：US06414396B1
公开(公告)日：2002-07-02
申请号：US09490317
申请日：2000-01-24
申请人： Il Kwon Shim , Vincent DiCaprio , Paul Hoffman , Byung Joon Han
发明人： Il Kwon Shim , Vincent DiCaprio , Paul Hoffman , Byung Joon Han
IPC分类号： H01L2940
CPC分类号： H01L25/0657 , H01L23/3114 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/06135 , H01L2224/06136 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45164 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/73215 , H01L2224/73265 , H01L2224/83101 , H01L2224/85424 , H01L2224/85447 , H01L2224/92147 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/00014 , H01L2224/85 , H01L2224/83 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2924/00015
摘要： Embodiments of integrated circuit packages for housing a plurality of integrated circuits are disclosed, along with methods of making the packages. One integrated circuit package comprises a substrate having a first surface having first metallizations thereon, an opposite second surface, and a plurality of apertures between the first and second surfaces. A first integrated circuit having a first surface with first bond pads thereon and an opposite second surface is mounted on the second surface of the substrate so that the first bond pads are superimposed with an aperture. Each first bond pad is electrically connected by a first bond wire extending through the superimposing aperture to a first metallization. A second integrated circuit having a first surface with conductive second bond pads thereon is mounted on the second surface of the first integrated circuit. In particular, the first surface of the second integrated circuit is placed on the second surface of the first integrated circuit so that the second bond pads are superimposed with one or more of the apertures through the substrate. Each second bond pad is electrically connected by a second bond wire extending through the superimposing aperture to a first metallization.
摘要翻译：公开了用于容纳多个集成电路的集成电路封装的实施例以及制造封装的方法。一个集成电路封装包括具有其上具有第一金属化的第一表面，相对的第二表面以及第一和第二表面之间的多个孔的基板。具有第一表面的第一集成电路，其上具有第一接合焊盘并且相对的第二表面安装在基板的第二表面上，使得第一接合焊盘与孔重叠。每个第一接合焊盘通过延伸穿过叠加孔的第一接合线电连接到第一金属化。具有其上具有导电第二接合焊盘的第一表面的第二集成电路安装在第一集成电路的第二表面上。特别地，第二集成电路的第一表面被放置在第一集成电路的第二表面上，使得第二接合焊盘与通过衬底的一个或多个孔叠加。每个第二接合焊盘通过延伸穿过叠加孔的第二接合线电连接到第一金属化。

34. 发明授权

US06020219A Method of packaging fragile devices with a gel medium confined by a rim member 失效
标题翻译：用由边缘构件限定的凝胶介质包装脆弱装置的方法
公开(公告)号：US06020219A
公开(公告)日：2000-02-01
申请号：US939053
申请日：1997-09-26
申请人： Thomas Dixon Dudderar , Byung Joon Han , Venkataram Reddy Raju , George John Shevchuk
发明人： Thomas Dixon Dudderar , Byung Joon Han , Venkataram Reddy Raju , George John Shevchuk
IPC分类号： H01L21/58 , H01L23/04 , H01L23/24 , H01L21/52 , H01L21/54 , H01L21/56
CPC分类号： H01L24/83 , H01L23/04 , H01L23/24 , H01L24/32 , H01L2224/2919 , H01L2224/32057 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/8319 , H01L2224/83385 , H01L2224/8385 , H01L24/45 , H01L24/48 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/16195 , H01L2924/1627 , H01L2924/16315 , H01L2924/181 , H01L2924/19041 , H01L2924/19043
摘要： A fragile device, such as an integrated circuit chip or a multichip assembly, is packaged by first dispensing a sol surrounding the sides of the device. The sol is laterally confined by means of a rim member typically made of a pre-molded plastic material. The amount of the sol dispensed is not sufficient to run over the top of the rim member. The sol is then heated to form a gel. If desired, a cover member can be put into place onto the top surface of the rim member, for the purpose of additional mechanical protection of the fragile device, for example.
摘要翻译：通过首先分配围绕设备的侧面的溶胶来封装诸如集成电路芯片或多芯片组件的脆弱器件。通过通常由预成型塑料材料制成的边缘构件将溶胶横向限制。分配的溶胶的量不足以超过边缘构件的顶部。然后将溶胶加热形成凝胶。如果需要，例如，可以将盖构件放置在边缘构件的顶表面上，以便对脆弱装置进行额外的机械保护。

35. 发明授权

US5897334A Method for reproducing printed circuit boards for semiconductor packages including poor quality printed circuit board units and method for fabricating semiconductor packages using the reproduced printed circuit boards 失效
标题翻译：再现用于半导体封装的印刷电路板的方法，包括差的印刷电路板单元以及使用再现的印刷电路板制造半导体封装的方法
公开(公告)号：US5897334A
公开(公告)日：1999-04-27
申请号：US951062
申请日：1997-10-15
申请人： Sun Ho Ha , Young Wook Heo , Byung Joon Han
发明人： Sun Ho Ha , Young Wook Heo , Byung Joon Han
IPC分类号： H01L23/28 , H01L21/50 , H01L21/66 , H01L23/12 , H01L23/498 , H05K1/00 , H05K3/00 , H05K3/22 , H01L21/44
CPC分类号： H01L22/22 , H01L23/4985 , H01L24/97 , H05K3/0097 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K1/0393 , H05K2201/09063 , H05K2201/0909 , H05K2203/1545 , H05K3/0052 , H05K3/225
摘要： A method for reproducing a PCB strip for semiconductor packages, wherein a poor quality PCB unit included in the PCB strip is replaced with a normal quality one, thereby achieving a reduction in the amount of package materials used and an improvement in the process efficiency. The invention also provides a method for fabricating semiconductor packages using the PCB strip reproduction method. A desired portion of a poor quality PCB unit included in a PCB strip is cut out in such a manner that a cutting opening having a peripheral edge extending along the singulation line of the poor quality PCB unit or along a region defined between the singulation line and anti-bending slots of the poor quality PCB unit. In the cutting opening, a separate good quality PCB unit member having the same shape and size as the cutting opening is then fitted. Thus, it is possible to simply and efficiently replace PCB units determined to be of poor quality with separate good quality PCB unit members, respectively.
摘要翻译：一种用于再现用于半导体封装的PCB板的方法，其中包括在PCB板中的劣质PCB单元被正常的质量替换，从而实现所使用的封装材料的量的减少和工艺效率的提高。本发明还提供了一种使用PCB条带再现方法制造半导体封装的方法。包含在PCB带中的劣质PCB单元的期望部分以这样的方式被切出：具有周边边缘的切割开口沿着劣质PCB单元的单线延伸，或者沿着限定在单线线和抗弯槽的质量差的PCB单元。在切割开口中，然后安装具有与切割开口相同的形状和尺寸的单独的优质PCB单元构件。因此，可以分别用单独的优质PCB单元构件简单有效地替代被确定为质量差的PCB单元。

36. 发明授权

US5834160A Method and apparatus for forming fine patterns on printed circuit board 失效
标题翻译：用于在印刷电路板上形成精细图案的方法和装置
公开(公告)号：US5834160A
公开(公告)日：1998-11-10
申请号：US586347
申请日：1996-01-16
申请人： Alan E. Ferry , Byung Joon Han , Maureen Yee Lau , Robert T. Scruton, Sr. , King Lien Tai
发明人： Alan E. Ferry , Byung Joon Han , Maureen Yee Lau , Robert T. Scruton, Sr. , King Lien Tai
IPC分类号： G03F7/20 , H05K3/00 , H05K3/06 , G03C5/00 , G03B27/52
CPC分类号： G03F7/70216 , G03F7/2002 , G03F7/70241 , G03F7/70791 , H05K3/0082
摘要： The present inventors have discovered that fine patterns of metal or insulator can be formed on printed circuit board using conventional lithographic steppers with inverted projection lenses. The inverted projection lenses act as enlargement lenses rather than reducing lenses and exhibit a large depth of focus sufficient to accommodate the deviations of PC board from planarity. The inverted lens reduces the size of the image needed at the mask, permitting multiple mask levels to be combined on a single glass. This reduces the cost of the mask set and permits the use of smaller glass masks having greater accuracy and dimensional stability than the convention mylar masks used for PC board. By inverting the projection lenses on near-obsolete steppers, applicants were able to form metal patterns on PC board of finer dimension than heretofore reported. Inverting a 5.times. ZEISS lens on a GCA 6300A stepper, applicants were able to form vias of less than 25 .mu.m diameter, pattern metal lines and spaces of less than 25 .mu.m, and obtain overlay registration accuracy of less than 25 .mu.m. The field size was larger than 1 in.sup.2, and the depth of focus was greater than 50 .mu.m.
摘要翻译：本发明人已经发现，使用具有倒置投影透镜的常规光刻步进器可以在印刷电路板上形成金属或绝缘体的精细图案。反转的投影透镜作为放大透镜而不是减少透镜并且展现出足够的焦深以适应PC板与平面度的偏差。倒置的镜头减少了掩模所需的图像的尺寸，允许在单个玻璃上组合多个掩模级别。这降低了掩模组的成本，并且允许使用比用于PC板的常规聚酯薄膜掩模更大的精度和尺寸稳定性的较小的玻璃面罩。通过将投影镜片倒置在近陈旧的步进器上，申请人能够在PC板上形成比迄今报告的更细的尺寸的金属图案。将5x蔡司镜头倒置在GCA 6300A步进机上，申请人能够形成直径小于25微米的通孔，图案金属线和小于25微米的间隙，并获得小于25微米的覆盖对准精度。场尺寸大于1 in2，焦点深度大于50m。

37. 发明授权

US5646828A Thin packaging of multi-chip modules with enhanced thermal/power management 失效
标题翻译：具有增强的热/电源管理的多芯片模块的薄封装
公开(公告)号：US5646828A
公开(公告)日：1997-07-08
申请号：US697121
申请日：1996-08-20
申请人： Yinon Degani , Thomas Dixon Dudderar , Byung Joon Han , Alan Michael Lyons
发明人： Yinon Degani , Thomas Dixon Dudderar , Byung Joon Han , Alan Michael Lyons
IPC分类号： H01L25/18 , H01L23/13 , H01L23/14 , H01L23/24 , H01L23/367 , H01L23/538 , H01L25/04 , H01L25/065 , H01L25/07 , H01L25/16 , H05K1/14 , H05K1/18 , H05K7/20
CPC分类号： H01L25/162 , H01L23/13 , H01L23/147 , H01L23/24 , H01L23/3677 , H01L23/5385 , H01L25/0655 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L24/48 , H01L2924/00014 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/16195 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/3025 , H05K1/141 , H05K1/142 , H05K1/182
摘要： A novel packaging of semiconductor elements, such as MCM tiles, with a variety of printed circuit or wired boards (PWB), the packages occupying a small size, at least in the vertical direction, relative to prior art OMPAC devices. The MCM tile includes an interconnection substrate with peripheral metallizations and at least one chip or integrated circuit (IC) mounted on the substrate by solder reflow or conductive adhesive technology. The PWB which may be a single level or a multilevel, is provided with an aperture for accommodation of at least one chip therein. Depending on the type of interconnection between the substrate and the PWB, the aperture may be larger than the substrate of the MCM tile for wire bonding interconnection or smaller than the substrate for solder reflow or conductive adhesive interconnection. In the wire bonding case, the MCM tile is positioned within the aperture resting on the surface of the PWB or of a structural member or of a heat sink which encloses one end of the aperture. The other end of the aperture may be open or enclosed by a structural member, a heat sink, another PWB or a mother board. For solder reflow or conductive adhesive interconnection, the substrate which is larger than the aperture is positioned so that its ends overlap areas of the PWB adjacent the aperture and the chips and/or substrate are positioned within the aperture. The interconnections are enclosed in a compliable encapsulating material, such as silica gel.
摘要翻译：相对于现有技术的OMPAC设备，至少在垂直方向上具有小尺寸的半导体元件（例如MCM瓦片）与各种印刷电路板或布线板（PWB）的新型封装。 MCM瓦片包括具有外围金属化的互连基板和通过焊料回流或导电粘合技术安装在基板上的至少一个芯片或集成电路（IC）。可以是单级或多级的PWB设置有用于在其中容纳至少一个芯片的孔。根据基板和PWB之间的互连类型，孔径可能大于用于引线接合互连的MCM瓦片的基板，或者小于用于焊料回流或导电粘合剂互连的基板。在引线接合壳体中，MCM瓦片位于留在PWB的表面上的孔内，或者围绕孔的一端的结构构件或散热器。孔的另一端可以由结构构件，散热器，另一PWB或母板打开或封闭。对于焊料回流或导电粘合剂互连，大于孔的衬底被定位成使得其端部与邻近孔的重叠区域重叠，并且芯片和/或衬底位于孔内。互连被封装在可复制的封装材料中，例如硅胶。

38. 发明申请

US20120286429A1 Semiconductor Device and Method of Singulating Thin Semiconductor Wafer on Carrier Along Modified Region Within Non-Active Region Formed by Irradiating Energy 有权
标题翻译：半导体器件和方法，通过辐射能形成非活动区域内的改性区域上载体上的薄半导体晶片
公开(公告)号：US20120286429A1
公开(公告)日：2012-11-15
申请号：US13469754
申请日：2012-05-11
申请人： Byung Joon Han , Il Kwon Shim , Won Kyoung Choi
发明人： Byung Joon Han , Il Kwon Shim , Won Kyoung Choi
IPC分类号： H01L23/498 , H01L21/78
CPC分类号： H01L21/6836 , H01L21/6835 , H01L21/78 , H01L23/481 , H01L23/544 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2221/68327 , H01L2221/6834 , H01L2221/68354 , H01L2221/68381 , H01L2223/5446 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0401 , H01L2224/0557 , H01L2224/05571 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/1132 , H01L2224/11334 , H01L2224/1146 , H01L2224/13023 , H01L2224/13025 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/81903 , H01L2224/9211 , H01L2224/94 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2224/03 , H01L2224/11 , H01L2924/00012 , H01L2924/01082 , H01L2924/0105 , H01L2924/00 , H01L2224/81 , H01L2224/83 , H01L2224/83851 , H01L2224/05552 , H01L2224/81805
摘要： A semiconductor device comprises a carrier including an adhesive disposed over the carrier. The semiconductor device further comprises a semiconductor wafer including a plurality of semiconductor die separated by a non-active region. A plurality of bumps is formed over the semiconductor die. The semiconductor wafer is mounted to the carrier with the adhesive disposed around the plurality of bumps. Irradiated energy is applied to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die. The semiconductor wafer is singulated along the modified region by applying stress to the semiconductor wafer. The adhesive is removed from around the plurality of bumps after singulating the semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor die comprising through silicon vias. The modified region optionally includes a plurality of vertically stacked modified regions.
摘要翻译：半导体器件包括载体，载体包括设置在载体上的粘合剂。半导体器件还包括半导体晶片，其包括由非有源区分隔的多个半导体管芯。在半导体管芯上形成多个凸点。半导体晶片被安装到载体上，粘合剂设置在多个凸起周围。照射能量被施加到非有源区域以在非活性区域内形成修饰区域。半导体晶片沿着改质区域分割成半导体管芯。通过向半导体晶片施加应力，沿着改质区域将半导体晶片分离。在分离半导体晶片之后，从多个凸起周围除去粘合剂。半导体晶片包括通过硅通孔的多个半导体管芯。修改区域可选地包括多个垂直堆叠的改性区域。

39. 发明授权

US08309397B2 Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof 有权
标题翻译：具有密封腔内的部件的集成电路封装系统及其制造方法
公开(公告)号：US08309397B2
公开(公告)日：2012-11-13
申请号：US13235755
申请日：2011-09-19
申请人： Il Kwon Shim , Byung Joon Han , Kambhampati Ramakrishna , Seng Guan Chow
发明人： Il Kwon Shim , Byung Joon Han , Kambhampati Ramakrishna , Seng Guan Chow
IPC分类号： H01L21/00 , H01L23/02 , H05K1/11
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/3135 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/18 , H01L31/0203 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00011 , H01L2924/00014 , H01L2924/01067 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for fabricating an encapsulant cavity integrated circuit package system includes: providing an interposer; forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and the interposer; and attaching a component on the interposer in the encapsulant cavity.
摘要翻译：一种用于制造密封腔的集成电路封装系统的方法，包括：提供插入器; 形成第一集成电路封装，其具有具有封装腔的反向底部端子和所述插入件; 以及将组件附接到所述密封剂腔中的所述插入件上。

40. 发明申请

US20120146192A1 INTEGRATED CIRCUIT MOUNTING SYSTEM WITH PADDLE INTERLOCK AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：集成电路安装系统及其制造方法
公开(公告)号：US20120146192A1
公开(公告)日：2012-06-14
申请号：US12967223
申请日：2010-12-14
申请人： Byung Joon Han , Byung Tai Do , Arnel Senosa Trasporto , Henry Descalzo Bathan
发明人： Byung Joon Han , Byung Tai Do , Arnel Senosa Trasporto , Henry Descalzo Bathan
IPC分类号： H01L29/06 , H01L21/52
CPC分类号： H01L23/49503 , H01L23/49513 , H01L23/49582 , H01L24/32 , H01L2224/27013 , H01L2224/32245 , H01L2224/32257 , H01L2224/83385 , H01L2224/83439 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/14 , H01L2924/00
摘要： A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive.
摘要翻译：一种制造集成电路安装系统的方法包括：提供具有模具安装区域的组件侧的模板和具有多于几何形状的凹部; 在模具安装区域和凹部的一部分中施加粘合剂; 并将具有非活性侧的集成电路装置直接安装在粘合剂上。

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