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1. 发明授权

US06803254B2 Wire bonding method for a semiconductor package 有权
标题翻译：半导体封装的引线接合方法
公开(公告)号：US06803254B2
公开(公告)日：2004-10-12
申请号：US10423702
申请日：2003-04-25
申请人： Young Kuk Park , Byung Joon Han , Jae Dong Kim
发明人： Young Kuk Park , Byung Joon Han , Jae Dong Kim
IPC分类号： H01L2150
CPC分类号： H01L24/85 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L25/0655 , H01L25/0657 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/4847 , H01L2224/48479 , H01L2224/4848 , H01L2224/49113 , H01L2224/73265 , H01L2224/78301 , H01L2224/85051 , H01L2224/85181 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2224/4554
摘要： A wire bonding method for electrically interconnecting stacked semiconductor chips is disclosed. A substrate (e.g., printed circuit board or metal leadframe) is provided. Metal circuit patterns are provided outside of a chip mounting region of the substrate, and metal transfer patterns are provided proximate to the chip mounting region. Stacked semiconductor are disposed in the chip mounting region. Conductive wires are bonded between respective pads of one stacked chip and respective transfer patterns, and other conductive wires are bonded between respective pads of the other stacked chip and the same respective transfer patterns, thereby electrically connecting respective pads of the two chips through a pair of bond wires and an intermediate transfer pattern. The transfer patterns are separate from circuit patterns of the substrate. At least one of the first and second chips is electrically connected to some of the circuit patterns for external connection.
摘要翻译：公开了一种用于电连接叠层半导体芯片的引线接合方法。提供基板（例如，印刷电路板或金属引线框架）。金属电路图案设置在基板的芯片安装区域的外侧，金属转印图案设置在芯片安装区域附近。堆叠的半导体被布置在芯片安装区域中。导电线接合在一个堆叠芯片的各个焊盘和各自的传输图案之间，并且其它导电线被接合在另一堆叠芯片的相应焊盘和相同的各个传输图案之间，从而通过一对接合线和中间转印图案。转印图案与基板的电路图案分离。第一和第二芯片中的至少一个电连接到用于外部连接的一些电路图案。

2. 发明授权

US06642610B2 Wire bonding method and semiconductor package manufactured using the same 有权
公开(公告)号：US06642610B2
公开(公告)日：2003-11-04
申请号：US09745265
申请日：2000-12-20
申请人： Young Kuk Park , Byung Joon Han , Jae Dong Kim
发明人： Young Kuk Park , Byung Joon Han , Jae Dong Kim
IPC分类号： H01L2302
CPC分类号： H01L24/85 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L25/0655 , H01L25/0657 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/4847 , H01L2224/48479 , H01L2224/4848 , H01L2224/49113 , H01L2224/73265 , H01L2224/78301 , H01L2224/85051 , H01L2224/85181 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2224/4554
摘要： A semiconductor package including plural semiconductor chips, and a wire bonding step for electrically interconnecting the semiconductor chips, are disclosed. In an exemplary method, a substrate is provided. Conductive circuit patterns are provided outside of a chip mounting region of the substrate, and conductive transfer patterns are provided proximate to the chip mounting region. Chips are placed in the chip mounting region. Conductive wires are bonded between input/output pads of a first chip and respective transfer patterns, and other conductive wires are bonded between input/output pads of a second chip and the same transfer patterns, thereby electrically connecting respective input/output pads of the two chips through a pair of bond wires and an intermediate transfer pattern.

3. 发明授权

US07863723B2 Adhesive on wire stacked semiconductor package 有权
标题翻译：粘合剂在线堆叠半导体封装
公开(公告)号：US07863723B2
公开(公告)日：2011-01-04
申请号：US12317649
申请日：2008-12-23
申请人： Kwang Seok Oh , Jong Wook Park , Young Kuk Park , Byoung Youl Min
发明人： Kwang Seok Oh , Jong Wook Park , Young Kuk Park , Byoung Youl Min
IPC分类号： H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/85 , H01L23/13 , H01L23/16 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48472 , H01L2224/48479 , H01L2224/48599 , H01L2224/48699 , H01L2224/73265 , H01L2224/85051 , H01L2224/85986 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01057 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85186 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof.
摘要翻译：半导体封装及其制造方法具有基板。第一半导体芯片耦合到衬底的表面。第一半导体芯片本质上具有基本平坦的第一和第二表面。粘合剂层耦合到第一半导体芯片的第二表面。进一步提供第二半导体芯片，其具有基本上平坦的第一表面和第二表面。绝缘体耦合到第二半导体芯片的第一表面，以防止引线短路。第二半导体芯片通过耦合到其第一表面的绝缘体耦合到粘合剂层。

4. 发明授权

US07485490B2 Method of forming a stacked semiconductor package 有权
标题翻译：形成层叠半导体封装的方法
公开(公告)号：US07485490B2
公开(公告)日：2009-02-03
申请号：US11286970
申请日：2005-11-22
申请人： Kwang Seok Oh , Jong Wook Park , Young Kuk Park , Byoung Youl Min
发明人： Kwang Seok Oh , Jong Wook Park , Young Kuk Park , Byoung Youl Min
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L24/85 , H01L23/13 , H01L23/16 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48472 , H01L2224/48479 , H01L2224/48599 , H01L2224/48699 , H01L2224/73265 , H01L2224/85051 , H01L2224/85986 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01057 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85186 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： Disclosed is a stacking structure of semiconductor chips and semiconductor package using it, capable of achieving an electric insulation even if a conductive wire makes contact with a lower surface of an upper semiconductor chip, while reducing a total thickness thereof and preventing damage. The stacking structure has a substrate formed with a plurality of circuit patterns; a first semiconductor chip bonded to an upper surface of the substrate and having a first plane and a second plane formed with a plurality of input/output pads; a spacer bonded to the second plane of the first semiconductor chip; a second semiconductor chip having first and second planes, the second plane being formed with a plurality of input/output pads, the first plane being provided with an insulating member so as to allow the second semiconductor chip to be bonded to the spacer, a first conductive wire for connecting the input/output pads of the first semiconductor chip to the circuit patterns of the substrate; and a second conductive wire for connecting the input/output pads of the second semiconductor chip to the circuit patterns of the substrate.
摘要翻译：公开了半导体芯片的堆叠结构和使用它的半导体封装，即使导线与上半导体芯片的下表面接触而能够实现电绝缘，同时减小其总厚度并防止损坏。堆叠结构具有形成有多个电路图案的基板; 第一半导体芯片，其结合到所述基板的上表面并具有形成有多个输入/输出焊盘的第一平面和第二平面; 连接到第一半导体芯片的第二平面的间隔物; 具有第一和第二平面的第二半导体芯片，所述第二平面形成有多个输入/输出焊盘，所述第一平面设置有绝缘构件，以允许所述第二半导体芯片与所述间隔件接合，导线，用于将第一半导体芯片的输入/输出焊盘连接到衬底的电路图案; 以及用于将第二半导体芯片的输入/输出焊盘连接到衬底的电路图案的第二导线。

5. 发明授权

US08143727B2 Adhesive on wire stacked semiconductor package 有权
标题翻译：粘合剂在线堆叠半导体封装
公开(公告)号：US08143727B2
公开(公告)日：2012-03-27
申请号：US12927533
申请日：2010-11-16
申请人： Kwang Seok Oh , Jong Wook Park , Young Kuk Park , Byoung Youl Min
发明人： Kwang Seok Oh , Jong Wook Park , Young Kuk Park , Byoung Youl Min
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/28 , H01L23/02
CPC分类号： H01L24/85 , H01L23/13 , H01L23/16 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48472 , H01L2224/48479 , H01L2224/48599 , H01L2224/48699 , H01L2224/73265 , H01L2224/85051 , H01L2224/85986 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01057 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85186 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof.
摘要翻译：半导体封装及其制造方法具有基板。第一半导体芯片耦合到衬底的表面。第一半导体芯片本质上具有基本平坦的第一和第二表面。粘合剂层耦合到第一半导体芯片的第二表面。进一步提供第二半导体芯片，其具有基本上平坦的第一表面和第二表面。绝缘体耦合到第二半导体芯片的第一表面，以防止引线短路。第二半导体芯片通过耦合到其第一表面的绝缘体耦合到粘合剂层。

6. 发明申请

US20110089564A1 ADHESIVE ON WIRE STACKED SEMICONDUCTOR PACKAGE 有权
标题翻译：电线堆叠半导体封装
公开(公告)号：US20110089564A1
公开(公告)日：2011-04-21
申请号：US12927533
申请日：2010-11-16
申请人： Kwang Seok Oh , Jong Wook Park , Young Kuk Park , Byoung Youl Min
发明人： Kwang Seok Oh , Jong Wook Park , Young Kuk Park , Byoung Youl Min
IPC分类号： H01L23/498
CPC分类号： H01L24/85 , H01L23/13 , H01L23/16 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48472 , H01L2224/48479 , H01L2224/48599 , H01L2224/48699 , H01L2224/73265 , H01L2224/85051 , H01L2224/85986 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01057 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85186 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof.
摘要翻译：半导体封装及其制造方法具有基板。第一半导体芯片耦合到衬底的表面。第一半导体芯片本质上具有基本平坦的第一和第二表面。粘合剂层耦合到第一半导体芯片的第二表面。进一步提供第二半导体芯片，其具有基本上平坦的第一表面和第二表面。绝缘体耦合到第二半导体芯片的第一表面，以防止引线短路。第二半导体芯片通过耦合到其第一表面的绝缘体耦合到粘合剂层。

7. 发明申请

US20090134507A1 Adhesive on wire stacked semiconductor package 有权
标题翻译：粘合剂在线堆叠半导体封装
公开(公告)号：US20090134507A1
公开(公告)日：2009-05-28
申请号：US12317649
申请日：2008-12-23
申请人： Kwang Seok Oh , Jong Wook Park , Young Kuk Park , Byoung Youl Min
发明人： Kwang Seok Oh , Jong Wook Park , Young Kuk Park , Byoung Youl Min
IPC分类号： H01L23/52
CPC分类号： H01L24/85 , H01L23/13 , H01L23/16 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48472 , H01L2224/48479 , H01L2224/48599 , H01L2224/48699 , H01L2224/73265 , H01L2224/85051 , H01L2224/85986 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01057 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85186 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof.
摘要翻译：半导体封装及其制造方法具有基板。第一半导体芯片耦合到衬底的表面。第一半导体芯片本质上具有基本平坦的第一和第二表面。粘合剂层耦合到第一半导体芯片的第二表面。进一步提供第二半导体芯片，其具有基本上平坦的第一表面和第二表面。绝缘体耦合到第二半导体芯片的第一表面，以防止引线短路。第二半导体芯片通过耦合到其第一表面的绝缘体耦合到粘合剂层。

8. 发明授权

US07260360B2 Multi-band ZigBee transceiver supporting IEEE 802.15.4 wireless communication 有权
标题翻译：支持IEEE 802.15.4无线通信的多频ZigBee收发器
公开(公告)号：US07260360B2
公开(公告)日：2007-08-21
申请号：US10981789
申请日：2004-11-05
申请人： Hae Moon Seo , Kwang Ho Won , Young Kuk Park , Myung Hyun Yoon , Jun Jae Yoo
发明人： Hae Moon Seo , Kwang Ho Won , Young Kuk Park , Myung Hyun Yoon , Jun Jae Yoo
IPC分类号： H04B7/00 , H04M1/00
CPC分类号： H04M1/72522 , H04B1/40 , H04M2250/06
摘要： Disclosed herein is a multi-band ZigBee transceiver for supporting IEEE 802.15.4 wireless communications. In the multi-band ZigBee transceiver, a Multi-Mode Modem (MMM) selects any one of a European version standard using 860 MHz band, a US version standard using 920 MHz band, and a worldwide version standard using 2.4 GHz ISM band among IEEE 802.15.4 standards. A frequency synthesizing unit variably adjusts a carrier frequency according to the transmission standard. A transmission unit receives a digital modulated signal, low-pass-filters the digital modulated signal with a bandwidth thereof being variably adjusted, and up-converts the filtered digital modulated signal into an RF modulated signal corresponding to the selected transmission channel. A receiving unit down-converts the RF modulated signal into a BB modulated signal using the carrier frequency, low-pass-filters the BB modulated signal with a bandwidth thereof being variably adjusted according to the selected transmission standard, converts the filtered BB modulated signal into a digital modulated signal, and outputs the digital modulated signal to the MMM. A transmission/reception switch unit outputs the RF modulated signal, input from the transmission unit, to an antenna, or outputs the RF modulated signal, received from the antenna, to the receiving unit.
摘要翻译：这里公开了一种用于支持IEEE 802.15.4无线通信的多频带ZigBee收发器。在多频ZigBee收发器中，多模式调制解调器（MMM）选择使用860 MHz频段的欧洲版本标准，使用920 MHz频段的美国版本标准和使用2.4 GHz ISM频段的全球版本标准 802.15.4标准。频率合成单元根据传输标准可变地调整载波频率。发送单元接收数字调制信号，对其数字调制信号进行可变调整的带宽的低通滤波，并且将滤波后的数字调制信号上变频为对应于选择的发送信道的RF调制信号。接收单元使用载波频率将RF调制信号下变频为BB调制信号，对BB调制信号进行低通滤波，其带宽根据选定的传输标准进行可变调整，将经过滤波的BB调制信号转换为数字调制信号，并将数字调制信号输出到MMM。发送/接收开关单元将从发送单元输入的RF调制信号输出到天线，或者将从天线接收的RF调制信号输出到接收单元。

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