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31. 发明授权

US06536008B1 Fault insertion method, boundary scan cells, and integrated circuit for use therewith 失效
标题翻译：故障插入方法，边界扫描单元和集成电路
公开(公告)号：US06536008B1
公开(公告)日：2003-03-18
申请号：US09181077
申请日：1998-10-27
申请人： Benoit Nadeau-Dostie , Jean-François Cote , Pierre Gauthier
发明人： Benoit Nadeau-Dostie , Jean-François Cote , Pierre Gauthier
IPC分类号： G01R3128
CPC分类号： G01R31/318583 , G01R31/318541
摘要： A number of fault injection circuits and corresponding methods for injecting correlated, uncorrelated, non-persistent and persisting faults at the primary outputs of boundary scan cells are disclosed. Fault data is loaded in the boundary scan cell update latch of all boundary scan cells at which a fault is to be injected. The fault injection circuits generate a fault inject signal which is applied to the control input of the standard cell output selector, an active signal causing the content of the update latch to be applied to the cell primary output. In order to provide for scan testing of the fault injection circuitry, the boundary scan cell shift and update latches and the fault flag latch (if employed) are provided with hold capability so that the contents of these elements can be controlled and their input captured in accordance with standard scan testing techniques.
摘要翻译：公开了一些故障注入电路和用于在边界扫描单元的主要输出处注入相关的，不相关的，非持久的和持续的故障的相应方法。故障数据将加载到要注入故障的所有边界扫描单元的边界扫描单元更新锁存器中。故障注入电路产生施加到标准单元输出选择器的控制输入的故障注入信号，使更新锁存器的内容被施加到单元初级输出的有效信号。为了提供故障注入电路的扫描测试，边界扫描单元移位和更新锁存器和故障标志锁存器（如果使用的话）被提供保持能力，使得这些元件的内容可以被控制并且其输入被捕获在符合标准扫描测试技术。

32. 发明授权

US06363520B1 Method for testability analysis and test point insertion at the RT-level of a hardware development language (HDL) specification 失效
标题翻译：在硬件开发语言（HDL）规范的RT级别进行可测试性分析和测试点插入的方法
公开(公告)号：US06363520B1
公开(公告)日：2002-03-26
申请号：US09098555
申请日：1998-06-16
申请人： Samir Boubezari , Eduard Cerny , Bozena Kaminska , Benoit Nadeau-Dostie
发明人： Samir Boubezari , Eduard Cerny , Bozena Kaminska , Benoit Nadeau-Dostie
IPC分类号： G06F1750
CPC分类号： G01R31/318583 , G01R31/318364
摘要： A method is provided for producing a synthesizable RT-Level specification, having a testability enhancement from a starting RT-Level specification representative of a circuit to be designed, for input to a synthesis tool to generate a gate-level circuit. The method includes the steps of performing a testability analysis on a Directed Acyclic Graph by computing and propagating Testability Measures forward and backward through VHDL statements, identifying the bits of each signal and/or variable, and adding test point statements into the specification at the RT-Level to improve testability of the circuit to be designed. The computation of Controllability and Observability method is purely functional, and does not subsume the knowledge of a gate-level implementation of the circuit being analyzed.
摘要翻译：提供了一种用于产生可综合RT-Level规范的方法，其具有代表要设计的电路的起始RT-Level规范的可测试性增强，用于输入到合成工具以产生门级电路。该方法包括以下步骤：通过VHDL语句向前和向后计算和传播可测度性测量，识别每个信号和/或变量的位，并将测试点语句添加到RT中的规范中，对定向非循环图进行可测试性分析提高设计电路的可测试性。可控性和可观察性方法的计算纯粹是功能性的，不包含所分析电路门级实现的知识。

33. 发明授权

US06330681B1 Method and apparatus for controlling power level during BIST 有权
标题翻译：在BIST期间控制功率电平的方法和装置
公开(公告)号：US06330681B1
公开(公告)日：2001-12-11
申请号：US09218764
申请日：1998-12-22
申请人： Jean-François Cote , Benoit Nadeau-Dostie , Pierre Gauthier
发明人： Jean-François Cote , Benoit Nadeau-Dostie , Pierre Gauthier
IPC分类号： G06F132
CPC分类号： G06F1/3203 , G01R31/318552
摘要： An improvement in a method of testing a digital circuit or system, having a plurality of scannable memory elements, in accordance with conventional BIST methods in which, at a reference clock, a test stimulus is shifted into the memory elements, the response of the elements is captured and the captured data is shifted out of the elements and analyzed, the improvement comprising controlling the average power consumption of the circuit during the test by suppressing clock pulses from the reference clock during phases of the test that do not require the maximum level of activity or in which the performance of the circuit is not to be evaluated; and, suppressing no clock pulses from the reference clock in phases of the test in which the performance of the circuit is to be evaluated, so that the conditions are substantially as those of normal mode of operation of the circuit.
摘要翻译：根据传统的BIST方法，测试具有多个可扫描存储器元件的数字电路或系统的测试方法的改进，其中在参考时钟将测试激励转移到存储器元件中，元件的响应并且捕获的数据被移出元件并被分析，改进包括在测试期间通过抑制来自参考时钟的时钟脉冲来控制电路的平均功耗，该阶段不需要最大等级活动或电路的性能不被评估; 并且在要评估电路的性能的测试阶段不抑制来自参考时钟的时钟脉冲，使得条件基本上与电路的正常工作模式相同。

34. 发明授权

US6115827A Clock skew management method and apparatus 有权
公开(公告)号：US6115827A
公开(公告)日：2000-09-05
申请号：US209790
申请日：1998-12-11
申请人： Benoit Nadeau-Dostie , Jean-Fran.cedilla.ois Cote
发明人： Benoit Nadeau-Dostie , Jean-Fran.cedilla.ois Cote
IPC分类号： G01R31/317 , G01R31/3185 , G06F1/10 , G06F1/04
CPC分类号： G01R31/31725 , G01R31/318552 , G01R31/318594 , G06F1/10
摘要： A method of testing an integrated circuit having core logic with two or more clock domains and at least one signal path originating in one clock domain and terminating in an other clock domain, each signal path having a source control element in the one clock domain and an associated destination control element in the other clock domain, each the control element being a scannable memory element, the method comprising the steps of, for each the control element shifting a test stimulus into all scannable elements in the core logic; placing an associated source control element in a hold mode for a predetermined number of clock cycles prior to a capture operation so that the source control element holds its output constant during the predetermined number of clock cycles; performing a capture operation for capturing the data output in response to the test stimulus by the control element and by all other scannable elements which are not control elements; maintaining an associated source control element in a hold mode for a predetermined number of clock cycles following a capture operation so that the source control element holds its output constant during the predetermined number of clock cycles; shifting out data captured in the capturing step; and analyzing the data captured in the capturing step. An integrated circuit for use with the method comprises a source control element and an associated destination control associated with each signal path for exchanging data between the one and the other of the clock domains, the source control element being located in the one clock domain and the associated destination element being located in the other domain; each control element being a scannable memory element having an input and an output and being configurable a SHIFT mode for shifting data from its input to its output and a CAPTURE mode for capturing data applied its input, each the source control element being further configurable in a HOLD mode for holding its output constant; and the control elements being configurable in the modes in response to predetermined combinations of a Scan Enable signal for enabling or disabling shifting of data therethrough and a Capture Disable signal having a one value to cause a recipient control element to enable the capture mode and another value to cause a recipient control element to suppress the capture mode.

35. 发明授权

US5923676A Bist architecture for measurement of integrated circuit delays 失效
标题翻译：用于测量集成电路延迟的Bist架构
公开(公告)号：US5923676A
公开(公告)日：1999-07-13
申请号：US771302
申请日：1996-12-20
申请人： Stephen K. Sunter , Benoit Nadeau-Dostie
发明人： Stephen K. Sunter , Benoit Nadeau-Dostie
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/31858
摘要： A built-in self-test (BIST) method and apparatus for digital integrated circuits (ICs) and for systems including multiple ICs, measures signal propagation delays in combinational and sequential logic, set-up and hold times, and tri-state enable/disable times, from any circuit node to any other circuit node including pin-to-pin and from one IC to another. The IC under test is provided with two test bus conductors passing near every circuit node of interest and connected thereto by switches or buffers. During test, an oscillator is created including the test bus, a constant delay, counters, and a delay path of interest or a reference path. The delay path of interest may include e.g. an analog filter. The oscillation period of the oscillator when the reference path is selected is subtracted from the oscillation period when the oscillator includes a delay path of interest. A circuit automatically accommodates inverting and non-inverting paths. A delay copier copies the delay between any two signal events, without injecting any test signal into the circuit under test (e.g. on-line test), and the delay copy can be measured by selecting it in the oscillator.
摘要翻译：用于数字集成电路（IC）和包括多个IC的系统的内置自测（BIST）方法和装置，测量组合和顺序逻辑中的信号传播延迟，建立和保持时间，以及三态使能/ 禁止时间，从任何电路节点到包括引脚到引脚和从一个IC到另一个的任何其他电路节点。被测试的IC设有两个测试总线导体，通过靠近感兴趣的每个电路节点并通过开关或缓冲器与其连接。在测试期间，创建振荡器，包括测试总线，恒定延迟，计数器和感兴趣的延迟路径或参考路径。感兴趣的延迟路径可以包括例如模拟滤波器。当振荡器包括感兴趣的延迟路径时，从振荡周期中减去当选择参考路径时振荡器的振荡周期。电路自动适应反相和非反相路径。延迟复印机复制任何两个信号事件之间的延迟，而不将任何测试信号注入被测电路（例如在线测试），并且延迟复制可以通过在振荡器中选择来测量。

36. 发明授权

US5323400A Scan cell for weighted random pattern generation and method for its operation 失效
标题翻译：用于加权随机模式生成的扫描单元及其操作方法
公开(公告)号：US5323400A
公开(公告)日：1994-06-21
申请号：US756703
申请日：1991-09-09
申请人： Vinod Agarwal , Benoit Nadeau-Dostie , Fidel Muradali
发明人： Vinod Agarwal , Benoit Nadeau-Dostie , Fidel Muradali
IPC分类号： G01R31/3183 , G01R31/3185 , H04B17/00
CPC分类号： G01R31/318385 , G01R31/318547
摘要： A scan cell comprises a flip-flop, a mode selector and a weighting network. The mode selector responds to a mode-select signal by selectively applying a circuit data input signal or a scan data input signal to a data input of the flip-flop. The weighting network responds to one logic state of a weight-select signal by applying a circuit data signal substantially identical to a scan data output signal appearing at a scan data output of the flip-flop to a circuit data output. The weighting network responds to another logic state of the weightselect signal by applying a circuit data output signal having a predetermined ratio of occurrences of one logic state to occurrences of another logic state to the circuit data output. The scan cell is used for generating weighted random patterns in scan chains for scan testing digital systems.
摘要翻译：扫描单元包括触发器，模式选择器和加权网络。模式选择器通过选择性地将电路数据输入信号或扫描数据输入信号施加到触发器的数据输入端来响应模式选择信号。加权网络通过将出现在触发器的扫描数据输出端的扫描数据输出信号基本上相同的电路数据信号施加到电路数据输出来响应加权选择信号的一个逻辑状态。加权网络通过将具有一个逻辑状态的预定出现比例的电路数据输出信号与另一个逻辑状态的出现相对于电路数据输出来响应于权重选择信号的另一个逻辑状态。扫描单元用于在扫描测试数字系统的扫描链中产生加权随机模式。

37. 发明授权

US4996691A Integrated circuit testing method and apparatus and integrated circuit devices for use therewith 失效
标题翻译：集成电路测试方法和装置以及集成电路装置
公开(公告)号：US4996691A
公开(公告)日：1991-02-26
申请号：US247258
申请日：1988-09-21
申请人： Philip S. Wilcox , Benoit Nadeau-Dostie , Vinod K. Agarwal
发明人： Philip S. Wilcox , Benoit Nadeau-Dostie , Vinod K. Agarwal
IPC分类号： G01R31/3185
CPC分类号： G01R31/318536 , G01R31/318566
摘要： In a so-called "scan-design" arrangement for testing integrated circuits, whether at the device level or at system level, problems associated with the storage and handling of vast amounts of data from increasingly complex devices are addressed by testing a pair of identical integrated circuits simultaneously and using the binary vector generated by scanning one of these integrated circuits as the reference against which to compare the binary vector produced by scanning the other integrated circuit. A plurality of "scan-designed" integrated circuits may be connected in series, possibly in a ring, and each compared with its predecessor. Zero-display coupling across each device may be employed to allow each successive integrated circuit to be compared with the same reference circuit in the chain or ring.
摘要翻译：在用于测试集成电路的所谓“扫描设计”布置中，无论是在设备级还是在系统级，与来自越来越复杂的设备的大量数据的存储和处理相关的问题通过测试一对相同的集成电路同时使用通过扫描这些集成电路之一而产生的二进制矢量作为比较通过扫描另一集成电路产生的二进制向量的参考。多个“扫描设计”集成电路可以串联连接，可能是环形的，并且每个集成电路与其前身相比较。可以采用跨每个器件的零显示耦合，以允许每个连续的集成电路与链或环中的相同参考电路进行比较。

38. 发明授权

US08516317B2 Methods for at-speed testing of memory interface 有权
标题翻译：存储器接口的高速测试方法
公开(公告)号：US08516317B2
公开(公告)日：2013-08-20
申请号：US13018279
申请日：2011-01-31
申请人： Benoit Nadeau-Dostie , Jean-François Côté
发明人： Benoit Nadeau-Dostie , Jean-François Côté
IPC分类号： G01R31/28
CPC分类号： G11C29/50012 , G11C8/16 , G11C29/1201 , G11C29/32
摘要： Methods for at-speed testing of a memory interface associated with an embedded memory comprise two write operations in succession, two read operations in succession, and a capture operation using scan cells. The write and read operations are performed during a single clock burst, two separate clock bursts in a clock signal, or two separate clock bursts in separate clock signals.
摘要翻译：用于速度测试与嵌入式存储器相关联的存储器接口的方法包括连续的两个写入操作，连续的两个读取操作以及使用扫描单元的捕获操作。写和读操作在单个时钟脉冲串期间执行，时钟信号中有两个独立的时钟脉冲串，或者在分离的时钟信号中执行两个分离的时钟脉冲串。

39. 发明申请

US20120272110A1 Test Generator For Low Power Built-In Self-Test 有权
标题翻译：用于低功耗内置自检的测试发生器
公开(公告)号：US20120272110A1
公开(公告)日：2012-10-25
申请号：US13451527
申请日：2012-04-19
申请人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Benoit Nadeau-Dostie
发明人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Benoit Nadeau-Dostie
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318575 , G01R31/31721 , G01R31/318385 , G01R31/3187
摘要： Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains.
摘要翻译：本发明的方面涉及基于BIST的低功率测试。低功率测试发生器可以包括伪随机模式发生器单元，触发控制单元，被配置为基于由伪随机模式发生器单元生成的比特序列数据产生切换控制数据;以及保持寄存器单元，被配置为产生低功率测试图案数据通过基于从触发控制单元接收到的切换控制数据，在各种时间段期间以常数值替换来自伪随机模式发生器单元的一些或全部输出的数据。低功率测试发生器还可以包括移相器，其被配置为组合用于驱动扫描链的低功率测试图案数据的位。

40. 发明授权

US07757135B2 Method and apparatus for storing and distributing memory repair information 有权
标题翻译：用于存储和分发存储器修复信息的方法和装置
公开(公告)号：US07757135B2
公开(公告)日：2010-07-13
申请号：US11853383
申请日：2007-09-11
申请人： Benoit Nadeau-Dostie , Jean-François Coté
发明人： Benoit Nadeau-Dostie , Jean-François Coté
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/4401 , G11C29/802 , G11C2029/0401 , G11C2029/4402 , G11C2229/726
摘要： A system for repairing embedded memories on an integrated circuit includes an external Built-In Self-repair Register (BISR) associated with every reparable memory. Each BISR is serially configured in a daisy chain with a fuse box controller. The controller determines the daisy chain length upon power up. The controller may perform a corresponding number of shift operations to move repair data between BISRs and a fuse box. Memories can have a parallel or serial repair interface. The BISRs may have a repair analysis facility into which fuse data may be dumped and uploaded to the fuse box or downloaded to repair the memory. Pre-designed circuit blocks provide daisy chain inputs and access ports to effect the system or to bypass the circuit block.
摘要翻译：用于在集成电路上修复嵌入式存储器的系统包括与每个可修复存储器相关联的外部内置自修复寄存器（BISR）。每个BISR以一个带有保险丝盒控制器的菊花链串行配置。控制器在上电时确定菊花链长度。控制器可以执行相应数量的换档操作，以在BISR和保险丝盒之间移动修理数据。存储器可以具有并行或串行修复界面。 BISR可能有一个维修分析设备，熔断器数据可能被转储并上传到保险丝盒或下载以修复存储器。预先设计的电路块提供菊花链输入和访问端口来影响系统或绕过电路块。

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