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    • 34. 发明授权
    • Method and apparatus for distributed load multiplexing of multiple encoded signals over a shared communication path
    • 用于通过共享通信路径分配负载复用多个编码信号的方法和装置
    • US07486732B1
    • 2009-02-03
    • US09907053
    • 2001-07-17
    • Paul DucharmeIndra Laksono
    • Paul DucharmeIndra Laksono
    • H04N7/12
    • H04N21/23655H04L65/607H04N19/61H04N21/2182
    • A method and apparatus for distributed load multiplexing of multiple encoded signals over a shared communication path include processing that begins by receiving a 1st encoded signal having a 1st varying relative bit rate. The processing continues by receiving a 2nd encoded signal having a 2nd varying relative bit rate. For example, the 1st and 2nd encoded signals may be an MPEG encoded signal including a plurality of I frames, B frames and P frames. The processing continues by aligning multiplexing of the 1st and 2nd encoded signals based on reducing cumulative peak bit rates of the 1st varying relative bit rate and the 2nd varying relative bit rate. For example, the 2nd encoded signal may be delayed via buffering to ensure that the I frames of the 1st and 2nd encoded signals are misaligned.
    • 用于通过共享通信路径分配负载复用多个编码信号的方法和装置包括通过接收具有第一变化相对比特率的第一编码信号开始的处理。 该处理通过接收具有第二变化相对比特率的第二编码信号而继续。 例如,第一和第二编码信号可以是包括多个I帧,B帧和P帧的MPEG编码信号。 该处理通过基于降低第一变化相对比特率和第二变化相对比特率的累积峰值比特率来对第一和第二编码信号的多路复用继续进行。 例如,可以经由缓冲来延迟第二编码信号,以确保第一和第二编码信号的I帧不对齐。
    • 37. 发明授权
    • Memory range access flags for performance optimization
    • 内存范围访问标志用于性能优化
    • US06778178B1
    • 2004-08-17
    • US09710943
    • 2000-11-13
    • Indra LaksonoDavid I. J. GlenPhilip J. RogersAnthony D. Scarpino
    • Indra LaksonoDavid I. J. GlenPhilip J. RogersAnthony D. Scarpino
    • G09G536
    • G09G5/001G09G5/363G09G5/39G09G2360/122
    • A graphic accelerator interface device for a computer is provided. The accelerator has a host data path that includes a plurality of comparators, each assigned to permit os/application access to a different “surface” which is defined by an address range corresponding to a block of data in a frame buffer. Unlike the prior art, an access flag register is associated with the host data path such that each surface assigned to a comparator has associated read and write flags. Whenever a read or a write occurs to one of the assigned surfaces via the host data path, the corresponding flag is set. Preferably, for os/application access, the surfaces contain data in an untiled format which the graphic accelerator uses in a tiled format. The invention affords more efficient, i.e. faster, processing, since the graphics driver can use prior tiled format data, if the write flag is clear, instead of processing the untiled data stored in an assigned surface into a useable tiled format which is only needed if the untiled data has been changed, i.e. indicted by the write flag being set.
    • 提供了一种用于计算机的图形加速器接口装置。 加速器具有包括多个比较器的主机数据路径,每个比较器被分配用于允许对与帧缓冲器中的数据块相对应的地址范围定义的不同“表面”的操作/应用访问。 与现有技术不同,访问标志寄存器与主机数据路径相关联,使得分配给比较器的每个表面具有相关联的读取和写入标志。 无论何时通过主机数据路径向其中一个分配的表面进行读取或写入,则设置相应的标志。 优选地,对于os /应用程序访问,表面包含图形加速器以平铺格式使用的直到格式的数据。 本发明提供更有效率,即更快的处理,因为图形驱动器可以使用先前的平铺格式数据,如果写入标志是清楚的,而不是将分配的表面中存储的直到数据处理成可用的平铺格式,只有如果 直到数据被改变,即由写入标志被设置指示。
    • 39. 发明授权
    • Method and apparatus for a graphics controller to extend graphics memory
    • 用于图形控制器扩展图形存储器的方法和装置
    • US06288729B1
    • 2001-09-11
    • US09259373
    • 1999-02-26
    • Indra LaksonoGordon Caruk
    • Indra LaksonoGordon Caruk
    • G06F1314
    • G06F3/14
    • A method and apparatus include processing which allows a graphics controller to extend its memory by receiving a client address and determining which of a plurality of system bus interfaces (e.g., AGP, PCI, ISA) is enabled. When a first type of system bus interface is enabled (e.g., PCI, ISA), a first system bus table index is generated based on the client address. The first system bus table index is used to access a first system bus table to retrieve a physical address of memory. The processing continues by obtaining data from the memory, wherein the data is stored at the physical address.
    • 一种方法和装置包括允许图形控制器通过接收客户端地址并确定多个系统总线接口(例如,AGP,PCI,ISA)中的哪一个被启用来扩展其存储器的处理。 当启用第一类型的系统总线接口(例如,PCI,ISA)时,基于客户端地址生成第一系统总线表索引。 第一系统总线表索引用于访问第一系统总线表以检索存储器的物理地址。 通过从存储器获取数据继续处理,其中数据存储在物理地址处。
    • 40. 发明授权
    • Method and apparatus for co-processing multi-formatted data
    • 用于协处理多格式数据的方法和装置
    • US5990910A
    • 1999-11-23
    • US47193
    • 1998-03-24
    • Indra LaksonoAnthony Asaro
    • Indra LaksonoAnthony Asaro
    • G06F9/30G06F9/38G06F15/16
    • G06F9/30025G06F9/3877
    • A method and apparatus for co-processing multi-formatted data which begins when a host processor writes data blocks, in a substantially continuous manner, into memory. Each of the data blocks includes a plurality of data elements and each data element has one of a plurality of data formats. As the data block is being stored in memory, a co-processor retrieves selected data elements from the memory. Upon retrieving the selected data elements, the co-processor interprets them to identify the data format. If the data format is consistent with the data format of the co-processor, the co-processor processes the data element without conversion. If, however, the data format of the selected data element is not consistent with the data format of the co-processor, the co-processor converts the format of the selected data element into the format consistent with the co-processor.
    • 一种用于协处理多格式数据的方法和装置,该方法和装置在主处理器以基本连续的方式将数据块写入存储器时开始。 每个数据块包括多个数据元素,并且每个数据元素具有多种数据格式之一。 当数据块被存储在存储器中时,协处理器从存储器中检索所选择的数据元素。 在检索所选择的数据元素之后,协处理器解释它们以识别数据格式。 如果数据格式与协处理器的数据格式一致,则协处理器处理数据元素而不进行转换。 然而,如果所选数据元素的数据格式与协处理器的数据格式不一致,则协处理器将所选择的数据元素的格式转换成与协处理器一致的格式。