专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06717987B1 Video compression method and apparatus employing error generation and error compression 有权
标题翻译：视频压缩方法和采用错误生成和错误压缩的装置
公开(公告)号：US06717987B1
公开(公告)日：2004-04-06
申请号：US09564963
申请日：2000-05-04
申请人： Anthony D. Scarpino , Arshad S. Rahman
发明人： Anthony D. Scarpino , Arshad S. Rahman
IPC分类号： H04N712
CPC分类号： H04N19/42 , G09G2340/02
摘要： A method and apparatus compresses digital information based on an interpolation function such as used by a graphic engine scaler. Luma error information is determined based on the interpolation function and original luma data. A luma error quantizer quantizes the luma error information to determine a quantized error value on a per pixel basis. The quantized luma error value is compressed as part of compressed video information. In addition, chroma information is also compressed and combined with the compressed luma and compressed error information. The video compression method and apparatus stores compressed digital luma information, compressed digital chroma information, and compressed quantized error information (values) as the compressed video information on a per frame basis.
摘要翻译：方法和装置基于诸如由图形引擎缩放器使用的内插函数压缩数字信息。基于内插函数和原始亮度数据确定亮度误差信息。亮度误差量化器量化亮度误差信息，以基于每像素确定量化的误差值。量化的亮度误差值被压缩为压缩视频信息的一部分。此外，色度信息也被压缩并与压缩的亮度和压缩的错误信息相结合。视频压缩方法和装置在每帧的基础上存储压缩数字亮度信息，压缩数字色度信息和压缩量化误差信息（值）作为压缩视频信息。

2. 发明授权

US06778178B1 Memory range access flags for performance optimization 有权
标题翻译：内存范围访问标志用于性能优化
公开(公告)号：US06778178B1
公开(公告)日：2004-08-17
申请号：US09710943
申请日：2000-11-13
申请人： Indra Laksono , David I. J. Glen , Philip J. Rogers , Anthony D. Scarpino
发明人： Indra Laksono , David I. J. Glen , Philip J. Rogers , Anthony D. Scarpino
IPC分类号： G09G536
CPC分类号： G09G5/001 , G09G5/363 , G09G5/39 , G09G2360/122
摘要： A graphic accelerator interface device for a computer is provided. The accelerator has a host data path that includes a plurality of comparators, each assigned to permit os/application access to a different “surface” which is defined by an address range corresponding to a block of data in a frame buffer. Unlike the prior art, an access flag register is associated with the host data path such that each surface assigned to a comparator has associated read and write flags. Whenever a read or a write occurs to one of the assigned surfaces via the host data path, the corresponding flag is set. Preferably, for os/application access, the surfaces contain data in an untiled format which the graphic accelerator uses in a tiled format. The invention affords more efficient, i.e. faster, processing, since the graphics driver can use prior tiled format data, if the write flag is clear, instead of processing the untiled data stored in an assigned surface into a useable tiled format which is only needed if the untiled data has been changed, i.e. indicted by the write flag being set.
摘要翻译：提供了一种用于计算机的图形加速器接口装置。加速器具有包括多个比较器的主机数据路径，每个比较器被分配用于允许对与帧缓冲器中的数据块相对应的地址范围定义的不同“表面”的操作/应用访问。与现有技术不同，访问标志寄存器与主机数据路径相关联，使得分配给比较器的每个表面具有相关联的读取和写入标志。无论何时通过主机数据路径向其中一个分配的表面进行读取或写入，则设置相应的标志。优选地，对于os /应用程序访问，表面包含图形加速器以平铺格式使用的直到格式的数据。本发明提供更有效率，即更快的处理，因为图形驱动器可以使用先前的平铺格式数据，如果写入标志是清楚的，而不是将分配的表面中存储的直到数据处理成可用的平铺格式，只有如果直到数据被改变，即由写入标志被设置指示。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式