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31. 发明授权

US07378898B2 Voltage droop suppressing circuit 失效
标题翻译：电压下降抑制电路
公开(公告)号：US07378898B2
公开(公告)日：2008-05-27
申请号：US11195554
申请日：2005-08-03
申请人： Rajendran Nair
发明人： Rajendran Nair
IPC分类号： H03K17/687
CPC分类号： G06F1/26 , H01L23/49811 , H01L23/50 , H01L23/5384 , H01L25/16 , H01L2224/16 , H01L2224/16235 , H01L2224/73253 , H01L2924/13091 , H01L2924/15312 , H01L2924/1532 , H01L2924/16152 , H01L2924/19106 , H01L2924/3011
摘要： The invention proposes noise suppression circuits that are assembled together with capacitors on a CPU package. Charge is conveyed from the capacitors dedicated to the active noise suppression function through electrical circuit pathways such as controlled electronic switches integrated into a semiconductor substrate. These circuit pathways connect to the capacitor terminals through the package of the active noise suppression semiconductor chip. The circuits within the active device may be any combination of semiconductor switches and/or voltage regulators, and may also contain voltage and current sensing circuitry. The charge transfer switches are designed with control circuitry that dynamically modulate the turn-on threshold voltage of the switches and maintain the switches at an operating point very close to actual turn-on. These enhancements ensure very fast turn-on action for the switches improving voltage droop suppression capability.
摘要翻译：本发明提出了在CPU封装上与电容器组装在一起的噪声抑制电路。通过诸如集成到半导体衬底中的受控电子开关的电路路径，从专用于有源噪声抑制功能的电容器传送电荷。这些电路通过有源噪声抑制半导体芯片的封装连接到电容器端子。有源器件内的电路可以是半导体开关和/或电压调节器的任何组合，并且还可以包含电压和电流检测电路。电荷转移开关设计有控制电路，其动态地调制开关的导通阈值电压，并将开关保持在非常接近实际开启的工作点。这些增强功能可确保开关的非常快的开启动作，从而提高电压下降抑制能力。

32. 发明授权

US07126387B2 Method and apparatus for driving low input impedance power transistor switches 失效
标题翻译：用于驱动低输入阻抗功率晶体管开关的方法和装置
公开(公告)号：US07126387B2
公开(公告)日：2006-10-24
申请号：US10794625
申请日：2004-03-08
申请人： Rajendran Nair
发明人： Rajendran Nair
IPC分类号： H03K3/00
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： An adaptable, low-power drive circuit for transistor switches requiring control input current is disclosed. In one embodiment of the invention, a current source output replaces the prior art voltage drive circuits and associated external current-limiting resistor. The current-source drive circuit provides both a high impedance as well as variability. The high impedance of the current-source drive circuit enables a reduction in the value of the resistance-bypass capacitor employed in the prior art. The variability in the output current provided by the current-source circuit allows the drive circuits to optimize the control current flowing into the switch device as the characteristics of the switch device change with operating temperature. The drive circuit is capable of providing as output either a desired current, at a high output impedance, or a desired voltage, at a low output impedance, employing a shared amplifier and output transistor. The drive circuit also derives current from the much lower output voltage of the buck conversion system that the invention is used in. This minimizes the static power dissipated in driving the switch, and also minimizes the energy expenditure incurred in increasing the output current to modulate the power switch resistance that increases with increasing temperature.
摘要翻译：公开了一种适用于需要控制输入电流的晶体管开关的低功耗驱动电路。在本发明的一个实施例中，电流源输出取代现有技术的电压驱动电路和相关的外部限流电阻。电流源驱动电路既提供高阻抗又具有可变性。电流源驱动电路的高阻抗使得能够减小现有技术中使用的电阻旁路电容器的值。由电流源电路提供的输出电流的变化允许驱动电路优化流入开关器件的控制电流，因为开关器件的特性随着工作温度的变化而变化。采用共享放大器和输出晶体管，驱动电路能够以低输出阻抗提供输出期望电流，高输出阻抗或期望电压。驱动电路还从使用本发明的降压转换系统的低得多的输出电压导出电流，这最大限度地减少了驱动开关时消耗的静态功耗，并且还最大限度地减少了增加输出电流以调制功率开关电阻随温度升高而增加。

33. 发明授权

US07053481B2 High capacitance package substrate 有权
公开(公告)号：US07053481B2
公开(公告)日：2006-05-30
申请号：US10703318
申请日：2003-11-07
申请人： Rajendran Nair
发明人： Rajendran Nair
IPC分类号： H01L23/06
CPC分类号： H05K1/162 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L2224/16 , H01L2924/01019 , H05K1/053 , H05K3/445 , H05K2201/0187
摘要： A high capacitance substrate. The substrate includes a core tolerant to sintering thereon of a high k material to provide increased capacitance. The core may be non-ceramic. The material sintered thereon may have a dielectric constant in excess of about 4. The substrate may be a package substrate electrically coupled to a die.

34. 发明申请

US20050168890A1 Method & apparatus for transient suppressing high-bandwidth voltage regulation 审中-公开
标题翻译：用于瞬态抑制高带宽电压调节的方法和装置
公开(公告)号：US20050168890A1
公开(公告)日：2005-08-04
申请号：US10766270
申请日：2004-01-29
申请人： Rajendran Nair
发明人： Rajendran Nair
IPC分类号： G06F1/26 , H01F17/00 , H01F19/00 , H01F27/42 , H02H7/00 , H02M3/158
CPC分类号： H02M3/1584 , G06F1/26 , H01F17/0006 , H01F19/00 , H01F27/42
摘要： A high-bandwidth, transient suppressing voltage down-converter apparatus and a method for transient suppression in such converters is disclosed. The invention is an integrated voltage converter electronic circuit, comprising of a first switch device connecting to an input power node at one of it's channel terminals and to a first integrated inductor at the other, with the first inductor's second terminal connecting to an output node, where this series combination of the first switch and the first inductor is a portion of an integrated voltage down-converter, a bypass circuit path, formed by a second switch device, or a series combination of a second switch device equivalent to the first switch device and a second inductor of the same self-inductance value as the first inductor, where the bypass circuit path connects between the input power node and the output power node of the integrated circuit in an electrically parallel configuration with the series combination of the first switch and the first inductor, voltage conversion circuits and conversion-bypass control circuits, receiving a plurality of signals as input, and connecting to the power input and output nodes of the integrated circuit as well as the control inputs of the first and second switch devices, and a common semiconductor substrate upon which the first switch device, the second switch device, necessary voltage conversion and control circuits, the first inductor, and the second inductor are fabricated.
摘要翻译：公开了一种高带宽瞬态抑制电压下变频器装置和这种转换器中的瞬态抑制方法。本发明是一种集成电压转换器电子电路，包括：第一开关装置，其连接到其一个通道端子处的输入功率节点，另一个连接到第一集成电感器，第一电感器的第二端子连接到输出节点，其中第一开关和第一电感器的串联组合是集成电压下变频器的一部分，由第二开关装置形成的旁路电路路径或等效于第一开关装置的第二开关装置的串联组合以及与第一电感器相同的自感值的第二电感器，其中旁路电路路径以电并联配置连接在输入功率节点和集成电路的输出功率节点之间，其中第一开关和第一电感器，电压转换电路和转换旁路控制电路，接收多个信号作为输入并连接到集成电路的电力输入和输出节点以及第一和第二开关装置的控制输入，以及公共半导体基板，第一开关装置，第二开关装置，必要的电压转换和控制电路，制造第一电感器和第二电感器。

35. 发明申请

US20050007163A1 Low jitter external clocking 审中-公开
标题翻译：低抖动外部时钟
公开(公告)号：US20050007163A1
公开(公告)日：2005-01-13
申请号：US10912486
申请日：2004-08-05
申请人： Rajendran Nair , Gregory Dermer , Stephen Mooney , Nitin Borkar
发明人： Rajendran Nair , Gregory Dermer , Stephen Mooney , Nitin Borkar
IPC分类号： G06F1/10 , H03K5/24 , H03B1/00
CPC分类号： G06F1/10 , H03K5/2481
摘要： A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.
摘要翻译：公开了一种低抖动外部时钟系统和方法。根据本发明的一个实施例，在第一时钟信号线和第二时钟信号线上接收差分时钟信号。耦合到第一时钟信号线和第二时钟信号线的差分放大器将差分时钟信号放大成单端输出时钟信号。

36. 发明授权

US06812757B2 Phase lock loop apparatus 失效
标题翻译：锁相环装置
公开(公告)号：US06812757B2
公开(公告)日：2004-11-02
申请号：US10146689
申请日：2002-05-14
申请人： Michael Pang-Cheng Hsu , Rajendran Nair , Stephen R. Mooney
发明人： Michael Pang-Cheng Hsu , Rajendran Nair , Stephen R. Mooney
IPC分类号： H03L706
CPC分类号： H03F3/45219 , H03D13/003 , H03F3/45183 , H03F2203/45318 , H03F2203/45394 , H03F2203/45674 , H03L7/091
摘要： A phase lock loop circuit including a voltage controlled oscillator and a phase detector having a sampling circuit and a linear voltage-to-current converter to create a control voltage for the voltage controlled oscillator. The phase lock loop circuit comprising a voltage-to-current circuit to influence a voltage on a capacitor, the voltage controlled oscillator responsive to the voltage on the capacitor, and the sampling circuit responsive to the first and second clock signals to generate two voltage values.
摘要翻译：一种锁相环电路，包括压控振荡器和具有采样电路和线性电压 - 电流转换器的相位检测器，以产生用于压控振荡器的控制电压。所述锁相环电路包括用于影响电容器上的电压的电压 - 电流电路，所述压控振荡器响应于所述电容器上的电压，所述采样电路响应于所述第一和第二时钟信号以产生两个电压值。

37. 发明授权

US06717445B1 Symmetric voltage follower buffer 有权
公开(公告)号：US06717445B1
公开(公告)日：2004-04-06
申请号：US09608086
申请日：2000-06-30
申请人： Rajendran Nair
发明人： Rajendran Nair
IPC分类号： H03B100
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A circuit including a signal input to receive a signal, a buffer circuit to receive the input signal and to generate a buffer circuit output, and a voltage following circuit to receive the signal input and to generate a voltage following output. The buffer circuit output and the voltage following circuit output are coupled to a circuit output node.

38. 发明授权

US06664834B2 Method for automatic duty cycle control using adaptive body bias control 失效
公开(公告)号：US06664834B2
公开(公告)日：2003-12-16
申请号：US09746211
申请日：2000-12-22
申请人： Rajendran Nair , Chantal E. Wright
发明人： Rajendran Nair , Chantal E. Wright
IPC分类号： H03K3017
CPC分类号： H03K5/1565
摘要： A method including sensing a duty cycle, measuring the variation of the duty cycle from a desired duty cycle, and differentially adjusting the rising and falling edges of the duty cycle is disclosed.

39. 发明授权

US06466473B2 Method and apparatus for increasing signal to sneak ratio in polarizable cross-point matrix memory arrays 失效
标题翻译：用于在极化交叉点矩阵存储器阵列中增加信号到潜行比的方法和装置
公开(公告)号：US06466473B2
公开(公告)日：2002-10-15
申请号：US09823690
申请日：2001-03-30
申请人： Rajendran Nair , David G. Chow
发明人： Rajendran Nair , David G. Chow
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A state of a memory element in a memory device is accessed by conditioning a number of wordlines and an addressed one of a number of bitlines in the memory device. This causes an addressed one of the memory elements in the device to release a signal charge and an unaddressed one to release a sneak charge into the addressed bitline. This charge release causes the current in the addressed bitline to increase. This current is integrated, and integration is halted when a signal to sneak ratio of the addressed bitline is maximized. The integration yields a total bitline charge value that may be used to obtain a more accurate measurement of the released signal charge.
摘要翻译：存储器件中的存储器元件的状态通过调节存储器件中的多个字线和寻址的多个位线之一来访问。这导致设备中寻址的一个存储器元件释放信号电荷和未寻址的释放电荷，以将潜行电荷释放到寻址的位线。该充电释放导致寻址位线中的电流增加。该电流被集成，并且当寻址位线的信号到潜行比最大化时，集成被停止。积分产生总位线电荷值，其可用于获得更准确的释放信号电荷的测量。

40. 发明授权

US06411151B1 Low jitter external clocking 有权
标题翻译：低抖动外部时钟
公开(公告)号：US06411151B1
公开(公告)日：2002-06-25
申请号：US09459783
申请日：1999-12-13
申请人： Rajendran Nair , Gregory E. Dermer , Stephen R. Mooney , Nitin Y. Borkar
发明人： Rajendran Nair , Gregory E. Dermer , Stephen R. Mooney , Nitin Y. Borkar
IPC分类号： G06F104
CPC分类号： G06F1/10 , H03K5/2481
摘要： A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.
摘要翻译：公开了一种低抖动外部时钟系统和方法。根据本发明的一个实施例，在第一时钟信号线和第二时钟信号线上接收差分时钟信号。耦合到第一时钟信号线和第二时钟信号线的差分放大器将差分时钟信号放大成单端输出时钟信号。

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