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31. 发明授权

US06555461B1 Method of forming low resistance barrier on low k interconnect 有权
标题翻译：在低k互连上形成低电阻势垒的方法
公开(公告)号：US06555461B1
公开(公告)日：2003-04-29
申请号：US09884059
申请日：2001-06-20
申请人： Christy Mei-Chu Woo , Suzette K. Pangrle , Minh Van Ngo
发明人： Christy Mei-Chu Woo , Suzette K. Pangrle , Minh Van Ngo
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76807 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate.
摘要翻译：用于形成金属互连结构的方法在电介质层的图案化开口内提供诸如氮化物之类的阻挡材料的共形层。在将开口蚀刻到电介质层上之后，阻挡材料沉积，停止在扩散阻挡层上。诸如钽的金属阻挡材料的第一层被共形沉积在阻挡材料上。执行定向蚀刻，其去除水平氮化物和钽，留下图案化开口的侧壁上的氮化物和钽。阻挡材料在覆盖导电材料的扩散阻挡层的蚀刻期间以及在随后的溅射蚀刻清洁期间防止介电层从导电材料（例如铜）中的污染。薄的第二金属层被共形沉积，并且在开口的侧壁上形成合适的阻挡层，同时在第二金属层和下面的基底之间提供低的接触电阻。

32. 发明授权

US06455422B1 Densification process hillock suppression method in integrated circuits 有权
标题翻译：集成电路中的致密化过程小丘抑制方法
公开(公告)号：US06455422B1
公开(公告)日：2002-09-24
申请号：US09705444
申请日：2000-11-02
申请人： Minh Van Ngo , Christy Mei-Chu Woo
发明人： Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76828 , H01L21/76883
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer of titanium, tantalum, tungsten, or a nitride of the aforegoing is deposited to line the opening, and a copper or copper alloy conductor core is deposited to fill the channel opening over the barrier layer. After planarization of the conductor core and the barrier layer, an ammonia, nitrogen hydride, or hydrogen plasma treatment is performed below 300° C. to reduce the residual oxide on the conductor core material. The plasma treatment is followed by the deposition of a silicon nitride capping layer performed below 300° C. After the reducing and deposition process, a densification process is performed between 380° C. and 420° C. to density the capping layer to enhance the quality of the silicon nitride layer.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体基板上形成器件电介质层，在器件电介质层上形成的沟道电介质层形成有开口部。沉积钛，钽，钨或前述氮化物的阻挡层以对开口进行排列，并且沉积铜或铜合金导体芯以填充阻挡层上的通道开口。在导体芯和阻挡层平坦化之后，在300℃以下进行氨，氮化氢或氢等离子体处理以减少导体芯材上的残余氧化物。等离子体处理之后，在300℃以下进行氮化硅覆盖层的沉积。在还原和沉积工艺之后，在380℃和420℃之间进行致密化过程以密封覆盖层以增强氮化硅层的质量。

33. 发明授权

US06387767B1 Nitrogen-rich silicon nitride sidewall spacer deposition 失效
标题翻译：富氮氮化硅侧壁间隔物沉积
公开(公告)号：US06387767B1
公开(公告)日：2002-05-14
申请号：US09781448
申请日：2001-02-13
申请人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
发明人： Paul R. Besser , Minh Van Ngo , Christy Mei-Chu Woo , George Jonathan Kluth
IPC分类号： H01L21336
CPC分类号： H01L29/665
摘要： Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.
摘要翻译：使用富含氮的氮化硅侧壁间隔物实现自杀处理，其允许使用硅化物技术在多晶硅栅极电极和源极/漏极区域上形成金属硅化物层，例如NiSi，而不会在栅极上的金属硅化物层之间相互桥接和源极/漏极区域之间的金属硅化物层。通过形成具有增加的富氮氮化硅侧壁间隔物，避免了金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的结合氮，从而消除可用于随后沉积的金属的游离Si，从而避免在侧壁间隔物上形成金属硅化物。

34. 发明授权

US07060571B1 Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric 有权
标题翻译：具有金属栅极和高k钽氧化物或氮氧化钽栅极电介质的半导体器件
公开(公告)号：US07060571B1
公开(公告)日：2006-06-13
申请号：US10777138
申请日：2004-02-13
申请人： Minh Van Ngo , Christy Woo , James Pan , Paul R. Besser , Jinsong Yin
发明人： Minh Van Ngo , Christy Woo , James Pan , Paul R. Besser , Jinsong Yin
IPC分类号： H01L21/336
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing a thin tantalum film, as by PVD at a thickness of 25 Å to 60 Å lining the opening, and then conducting thermal oxidation, as at a temperature of 100° C. to 500° C., in flowing oxygen or ozone to form a high-k tantalum oxide gate dielectric layer, or in oxygen and N2O or ozone and N2O ammonia to form a high-k tantalum oxynitride gate dielectric. Alternatively, oxidation can be conducted in an oxygen or ozone plasma to form the high-k tantalum oxide layer, or in a plasma containing N2O and oxygen or ozone to form the high-k tantalum oxynitride gate dielectric layer.
摘要翻译：微型半导体器件由具有显着降低的碳的替代金属栅极和高k钽氧化物或氮氧化钽栅极电介质制成。实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积薄的钽膜，如通过PVD覆盖厚度为25埃至60埃的开口，然后在100℃的温度下进行热氧化在500℃下，在流动的氧气或臭氧中形成高k氧化钽栅极电介质层，或在氧和N 2 O或臭氧和N 2 O 3 > O氨形成高k钽氮氧化物栅极电介质。或者，可以在氧气或臭氧等离子体中进行氧化以形成高k钽氧化物层，或者在含有N 2 O的氧化物或臭氧的等离子体中进行氧化以形成高k氮氧化钽栅极电介质层。

35. 发明授权

US09202758B1 Method for manufacturing a contact for a semiconductor component and related structure 有权
标题翻译：制造半导体元件用触点及其结构的方法
公开(公告)号：US09202758B1
公开(公告)日：2015-12-01
申请号：US11109965
申请日：2005-04-19
申请人： Paul R. Besser , Minh Van Ngo , Connie Pin-Chin Wang , Jinsong Yin , Hieu T. Pham
发明人： Paul R. Besser , Minh Van Ngo , Connie Pin-Chin Wang , Jinsong Yin , Hieu T. Pham
IPC分类号： H01L21/8234 , H01L29/49
CPC分类号： H01L21/823418 , H01L21/02129 , H01L21/02271 , H01L21/28556 , H01L21/28562 , H01L21/76801 , H01L21/76834 , H01L21/76843 , H01L21/76877 , H01L23/485 , H01L23/53266 , H01L23/53295 , H01L29/4975 , H01L29/665 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component and a method for manufacturing the semiconductor component that are suitable for use with low temperature processing. A semiconductor substrate is provided and an optional layer of silicon nitride is formed on the semiconductor substrate using Atomic Layer Deposition (ALD). A layer of dielectric material is formed on the silicon nitride layer using Sub-Atmospheric Chemical Vapor Deposition (SACVD) at a temperature below about 450° C. When the optional layer of silicon nitride is not present, the SACVD dielectric material is formed on the semiconductor substrate. A contact hole having sidewalls is formed through the SACVD dielectric layer, through the silicon nitride layer, and exposes a portion of the semiconductor substrate. A layer of tungsten nitride is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact hole. Tungsten is formed on the layer of tungsten nitride.
摘要翻译：适用于低温处理的半导体元件和半导体元件的制造方法。提供半导体衬底，并且使用原子层沉积（ALD）在半导体衬底上形成任选的氮化硅层。使用亚大气化学气相沉积（SACVD）在低于约450℃的温度下在氮化硅层上形成介电材料层。当不存在任选的氮化硅层时，SACVD介电材料形成在半导体衬底。通过SACVD介电层，通过氮化硅层形成具有侧壁的接触孔，并露出半导体衬底的一部分。在半导体衬底的暴露部分和接触孔的侧壁上形成氮化钨层。在氮化钨层上形成钨。

36. 发明授权

US07217660B1 Method for manufacturing a semiconductor component that inhibits formation of wormholes 有权
标题翻译：制造抑制虫洞形成的半导体部件的方法
公开(公告)号：US07217660B1
公开(公告)日：2007-05-15
申请号：US11109964
申请日：2005-04-19
申请人： Connie Pin-Chin Wang , Paul R. Besser , Jinsong Yin , Hieu T. Pham , Minh Van Ngo
发明人： Connie Pin-Chin Wang , Paul R. Besser , Jinsong Yin , Hieu T. Pham , Minh Van Ngo
IPC分类号： H01L21/22
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/28556 , H01L21/28562 , H01L21/76843 , H01L21/76846 , H01L29/6659
摘要： A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.
摘要翻译：一种制造半导体元件的方法，该半导体元件抑制在半导体衬底中形成虫洞。在设置在半导体衬底上的电介质层中形成接触开口。接触开口露出半导体衬底的一部分。在半导体衬底的暴露部分上并沿着接触开口的侧壁形成氧化物牺牲层。硅烷与六氟化钨反应形成氢氟酸蒸汽和钨。氢氟酸蒸气蚀刻掉牺牲氧化物层，并且在半导体衬底的暴露部分上形成薄的钨层。在形成钨的薄层之后，可以改变反应物以更快地用钨填充接触开口。

37. 发明授权

US07476604B1 Aggressive cleaning process for semiconductor device contact formation 有权
标题翻译：用于半导体器件接触形成的积极清洁工艺
公开(公告)号：US07476604B1
公开(公告)日：2009-01-13
申请号：US11128391
申请日：2005-05-13
申请人： Ning Cheng , Minh Van Ngo , Jinsong Yin , Paul Raymond Besser , Connie Pin-chin Wang , Russell Rosaire Austin Callahan , Jeffrey Shields , Shankar Sinha , Jeff P. Erhardt , Jeremy Chi-Hung Chou
发明人： Ning Cheng , Minh Van Ngo , Jinsong Yin , Paul Raymond Besser , Connie Pin-chin Wang , Russell Rosaire Austin Callahan , Jeffrey Shields , Shankar Sinha , Jeff P. Erhardt , Jeremy Chi-Hung Chou
IPC分类号： H01L21/44
CPC分类号： H01L21/76831 , H01L21/02063 , H01L21/28518 , H01L21/76814 , H01L21/76843 , H01L21/76855
摘要： A method of forming a contact through a material includes forming a via through a dielectric material and cleaning the via using a dilute hydrofluoric (DHF) acid solution. The method further includes depositing a barrier layer within the via and depositing metal adjacent the barrier layer.
摘要翻译：通过材料形成接触的方法包括通过电介质材料形成通孔，并使用稀氢氟酸（DHF）酸溶液清洗通孔。所述方法还包括在所述通孔内沉积阻挡层并在所述阻挡层附近沉积金属。

38. 发明授权

US07033888B2 Engineered metal gate electrode 有权
标题翻译：工程金属栅电极
公开(公告)号：US07033888B2
公开(公告)日：2006-04-25
申请号：US10806117
申请日：2004-03-23
申请人： James N. Pan , Paul R. Besser , Christy Woo , Minh Van Ngo , Jinsong Yin
发明人： James N. Pan , Paul R. Besser , Christy Woo , Minh Van Ngo , Jinsong Yin
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28088 , H01L29/4966
摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.
摘要翻译：形成具有固有电场的金属栅电极，以改变晶体管的功函数和阈值电压。实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积一层或多层氮化钽，使氮含量从邻近栅介质层的层的底部向上增加。其他实施例包括通过掺杂一个或多个金属层并形成金属合金来形成本征电场以控制功函数。实施例还包括在形成金属栅电极时使用阻挡层。

39. 发明授权

US06727560B1 Engineered metal gate electrode 有权
公开(公告)号：US06727560B1
公开(公告)日：2004-04-27
申请号：US10360719
申请日：2003-02-10
申请人： James N. Pan , Paul R. Besser , Christy Woo , Minh Van Ngo , Jinsong Yin
发明人： James N. Pan , Paul R. Besser , Christy Woo , Minh Van Ngo , Jinsong Yin
IPC分类号： H01L2976
CPC分类号： H01L29/66545 , H01L21/28088 , H01L29/4966
摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

40. 发明授权

US06258697B1 Method of etching contacts with reduced oxide stress 有权
标题翻译：蚀刻氧化应力减小接触的方法
公开(公告)号：US06258697B1
公开(公告)日：2001-07-10
申请号：US09502333
申请日：2000-02-11
申请人： Jayendra Bhakta , Paul Besser , Minh Van Ngo
发明人： Jayendra Bhakta , Paul Besser , Minh Van Ngo
IPC分类号： H01L2176
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02337 , H01L21/31612 , H01L21/76224
摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrate. Oxide is deposited as a trench liner in the trench using low pressure chemical vapor deposition (LPCVD) high temperature oxidation (HTO). As LPCVD is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overetch at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.
摘要翻译：半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。使用低压化学气相沉积（LPCVD）高温氧化（HTO）将氧化物作为沟槽衬垫沉积在沟槽中。由于LPCVD是应力中性过程，因此避免了硅衬底和氧化物层之间的界面中的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处过蚀刻。当局部互连形成时，这减少了结漏电的可能性。

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