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31. 发明授权

US09496008B1 Determination of a common mode voltage 有权
标题翻译：确定共模电压
公开(公告)号：US09496008B1
公开(公告)日：2016-11-15
申请号：US14729100
申请日：2015-06-03
申请人： International Business Machines Corporation
发明人： Matthias Braendli , Marcel A. Kossel
IPC分类号： G11C5/14 , G11C11/4074
CPC分类号： G11C5/147 , G11C7/14 , G11C11/4074 , G11C29/028
摘要： The invention relates to a receiving unit for performing a calibration of a reference voltage, comprising a reference voltage unit for generating and applying a reference voltage on the evaluation unit depending on a converter value, an evaluation unit for receiving a single-ended data signal and being configured to determine an evaluation signal based on the data signal and the reference voltage, and a logic unit configured to perform a calibration process for calibrating the reference voltage. The logic unit is configured to command a memory device to apply a permanent digital logical state on a data line, to iteratively adapt a converter voltage to substantially match the voltage level of the logical state on the data line, and to determine the reference voltage depending on the converter voltage for which the voltage level of the logical state on the data line has been substantially matched.
摘要翻译：本发明涉及一种用于执行参考电压校准的接收单元，包括用于根据转换器值在评估单元上产生和施加参考电压的参考电压单元，用于接收单端数据信号的评估单元和被配置为基于所述数据信号和所述参考电压来确定评估信号，以及逻辑单元，被配置为执行用于校准所述参考电压的校准处理。逻辑单元被配置为命令存储器件在数据线上施加永久数字逻辑状态，以迭代地适配转换器电压以使数据线上的逻辑状态的电压电平基本匹配，并且确定参考电压依赖在数据线上的逻辑状态的电压电平基本匹配的转换器电压上。

32. 发明申请

US20160087822A1 METHOD AND APPARATUS FOR GENERATING A MULTI-LEVEL PSEUDO-RANDOM TEST SIGNAL 有权
标题翻译：用于产生多级随机测试信号的方法和装置
公开(公告)号：US20160087822A1
公开(公告)日：2016-03-24
申请号：US14864447
申请日：2015-09-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Marcel A. Kossel
IPC分类号： H04L25/49
CPC分类号： H04L25/4917
摘要： The present invention relates to a method for generating multi-level PRBS patterns for testing purposes, wherein the method includes the steps of providing a binary PRBS signal with a binary bit pattern sequence and mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output.
摘要翻译：本发明涉及一种生成用于测试目的的多级PRBS模式的方法，其中该方法包括以下步骤：提供二进制位模式序列的二进制PRBS信号，并将二进制位模式序列的每一位映射到多级输出。

33. 发明公开

US20240346296A1 LOW-LATENCY TIME-ENCODED SPIKING NEURAL NETWORK 审中-公开
公开(公告)号：US20240346296A1
公开(公告)日：2024-10-17
申请号：US18299392
申请日：2023-04-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Giovanni Cherubini , Marcel A. Kossel
IPC分类号： G06N3/049 , G06N3/08
CPC分类号： G06N3/049 , G06N3/08
摘要： A method of executing a time-encoded spiking neural network (tSNN) that includes configuring an electronic circuit connecting pairs of neurons of the tSNN, wherein each pair of the pairs of neurons connects a sender neuron to a receiver neuron through parallel channels, and operating the electronic circuit at an actual clock rate corresponding to actual time steps, for the electronic circuit to perform signaling over said each pair at each time step of the actual time steps by sending signals in parallel across the parallel channels. Sent signals encode subcycle timing information about a timing of spikes relative to subcycle time steps, a unit duration that corresponds to a duration of said each time step divided by a latency reduction factor (LRF), for the operated electronic circuit to emulate an execution of the tSNN at an effective clock rate corresponding to the actual clock rate multiplied by the LRF.

34. 发明授权

US12095473B2 Time domain interleaving 有权
公开(公告)号：US12095473B2
公开(公告)日：2024-09-17
申请号：US18053940
申请日：2022-11-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Abdullah Serdar Yonar , Pier Andrea Francese , Marcel A. Kossel , Mridula Prathapan , Matthias Braendli , Thomas Morf
IPC分类号： H03M1/50 , H03M1/10 , H03M1/12
CPC分类号： H03M1/50 , H03M1/1009 , H03M1/1215 , H03M1/1245
摘要： The invention is notably directed to a voltage-to-time converter comprising a first interleaving stage configured to perform a sampling of an input voltage, thereby generating a first set of sampled voltage signals. The first interleaving stage is further configured to perform a first voltage-to-time conversion in an interleaved manner, thereby generating a first set of time-interleaved signals in the time domain. A second interleaving stage is configured to perform a time-to-voltage conversion of the first set of time-interleaved signals, thereby generating a second set of sampled voltage signals. The second interleaving stage is further configured perform a second voltage-to-time conversion in an interleaved manner, thereby generating a second set of time-interleaved signals in the time domain.
The invention further concerns a related design structure and a related method.

35. 发明公开

US20230403020A1 SEGMENTED DIGITAL-TO-ANALOG CONVERTER WIRELINE DRIVER 审中-公开
公开(公告)号：US20230403020A1
公开(公告)日：2023-12-14
申请号：US17839141
申请日：2022-06-13
申请人： International Business Machines Corporation
发明人： Martin Cochet , Marcel A. Kossel , John Francis Bulzacchelli , Timothy O. Dickson , Zeynep Toprak-Deniz
IPC分类号： H03M1/10
CPC分类号： H03M1/1014
摘要： An apparatus comprises one or more A-type resistance segments, wherein each A-type resistance segment comprises one or more A-type switches, at least one A-type linear resistor coupled to the one or more A-type switches, at least one A-type tunable header unit coupled to the one or more A-type switches, and at least one A-type tunable footer unit coupled to the one or more A-type switches; one or more B-type resistance segments, wherein each B-type resistance segment comprises one or more B-type switches, at least one B-type linear resistor coupled to at least a proper subset of the one or more B-type switches, at least one B-type tunable header unit coupled to the one or more B-type switches, and at least one B-type tunable footer unit coupled to the one or more B-type switches; and wherein second terminals of the A-type linear resistors and the B-type linear resistors are coupled together.

36. 发明授权

US11652493B2 Successive-approximation analog-to-digital converters 有权
公开(公告)号：US11652493B2
公开(公告)日：2023-05-16
申请号：US17354421
申请日：2021-06-22
申请人： International Business Machines Corporation
发明人： Abdullah Serdar Yonar , Pier Andrea Francese , Marcel A. Kossel
IPC分类号： H03M1/12 , H03M1/10 , H03M1/46
CPC分类号： H03M1/125 , H03M1/1009 , H03M1/462
摘要： A successive-approximation analog-to-digital converter includes a sampling circuit for sampling an analog input signal to acquire a sampled voltage, and a regenerative comparator for comparing the sampled voltage with a succession of reference voltages to generate, for each reference voltage, a decision bit indicating the comparison result. The converter also includes a digital-to-analog converter which is adapted to generate the succession of reference voltages, in dependence on successive comparison results in the comparator, to progressively approximate the sampled voltage. The regenerative comparator comprises an integration circuit for generating output signals defining the decision bits, and a plurality of regeneration circuits for receiving these output signals. The regeneration circuits are operable, in response to respective control signals, to store respective decision bits defined by successive output signals from the integration circuit.

37. 发明授权

US11621720B2 Quantum processing apparatus with downsampling analog-to-digital converter 有权
公开(公告)号：US11621720B2
公开(公告)日：2023-04-04
申请号：US17108469
申请日：2020-12-01
申请人： International Business Machines Corporation
发明人： Peter Mueller , Thomas Morf , Pier Andrea Francese , Marcel A. Kossel
IPC分类号： H03M1/12 , G06N10/00 , H01L27/18 , G01R33/035 , H03M1/66 , H04B10/70 , G06N10/40 , G01R33/24 , G01N24/12 , G01R33/32
摘要： Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M>1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the nth Nyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the nth Nyquist zone to the mth Nyquist zone of the spectrum, where n>m≥1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.

38. 发明授权

US11271550B1 Synchronous divider based on cascaded retiming 有权
公开(公告)号：US11271550B1
公开(公告)日：2022-03-08
申请号：US17302185
申请日：2021-04-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Marcel A. Kossel , Pier Andrea Francese , Mridula Prathapan , Abdullah Serdar Yonar
IPC分类号： H03K3/037 , H03L7/08 , G06F1/32
摘要： A synchronous divider circuit with time-synchronized outputs. The synchronous divider circuit includes a plurality of divider stages including each a D-flip-flop circuit and a respective retiming flip-flop circuit, wherein an output terminal of the retiming flip-flop circuit of a current divider stage is connected to an input of the D-flip-flop circuit of a next divider stage, and wherein the current divider stage includes an additional retiming flip-flop circuit, wherein the output terminal of the retiming flip-flop circuit of the current divider stage is connected to an input terminal of the additional retiming flip-flop circuit of the current divider stage, so that an output signal of the additional retiming flip-flop circuit of the current divider stage and an output terminal of the retiming flip-flop circuit of the next divider stage are time-synchronized with respect to each other.

39. 发明授权

US11095487B1 Operating a wireline receiver with a tunable timing characteristic 有权
公开(公告)号：US11095487B1
公开(公告)日：2021-08-17
申请号：US16850084
申请日：2020-04-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Abdullah Serdar Yonar , Pier Andrea Francese , Marcel A. Kossel
IPC分类号： H04B1/16 , H04L25/03
摘要： A method of operating a wireline receiver. The receiver may include a front-end comparator and a feedback controller. The method may include providing, by the front-end comparator, a symbol signal by processing a received electrical input signal according to a tunable timing characteristic of the front-end comparator. The method may further include adapting, by the feedback controller, the processing of the input signal to match a predetermined processing criterion by tuning the timing characteristic based on the symbol signal.

40. 发明申请

US20210175892A1 QUANTUM PROCESSING APPARATUS WITH DOWNSAMPLING ANALOG-TO-DIGITAL CONVERTER 有权
公开(公告)号：US20210175892A1
公开(公告)日：2021-06-10
申请号：US17108469
申请日：2020-12-01
申请人： International Business Machines Corporation
发明人： Peter Mueller , Thomas Morf , Pier Andrea Francese , Marcel A. Kossel
IPC分类号： H03M1/12 , G06N10/00
摘要： Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M>1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the nth Nyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the nth Nyquist zone to the mth Nyquist zone of the spectrum, where n>m≥1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.

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