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31. 发明授权

US07091563B2 Method and structure for improved MOSFETs using poly/silicide gate height control 失效
标题翻译：使用多晶硅/硅化物栅极高度控制的改进MOSFET的方法和结构
公开(公告)号：US07091563B2
公开(公告)日：2006-08-15
申请号：US11057126
申请日：2005-02-15
申请人： Dureseti Chidambarrao , Omer H. Dokumaci
发明人： Dureseti Chidambarrao , Omer H. Dokumaci
IPC分类号： H01L27/092
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/84
摘要： A method for manufacturing an integrated circuit that has a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor. This method involves depositing oxide fill on the n-type transistor and the p-type transistor and chemical/mechanical polishing the deposited oxide fill such that a gate stack of the n-type transistor and a gate stack of the p-type transistor, which each have spacers which are surrounded with oxide. The method further involves etching a portion of the polysilicon from a gate of the p-type field effect transistor, depositing a low resistance material (e.g., Co, Ni, Ti, or other similar metals) on the n-type field effect transistor and the p-type field effect transistor, and heating the integrated circuit such that the deposited material reacts with the polysilicon of the n-type transistor and the polysilicon of the p-type transistor to form silicide. The silicide formed on the p-type polysilicon imposes compressive mechanical stresses along the longitudinal direction of the channel of the p-type field effect transistor. A semiconductor device formed by this method has compressive stresses along the length of the PFET channel and tensile stresses along the length of the NFET channel.
摘要翻译：一种具有包括n型场效应晶体管和p型场效应晶体管的多个半导体器件的集成电路的制造方法。该方法包括在n型晶体管和p型晶体管上沉积氧化物填充物，并化学/机械抛光沉积的氧化物填充物，使得n型晶体管的栅极堆叠和p型晶体管的栅极堆叠，其中每个具有被氧化物包围的间隔物。该方法还包括从p型场效应晶体管的栅极蚀刻多晶硅的一部分，在n型场效应晶体管上沉积低电阻材料（例如，Co，Ni，Ti或其它类似的金属），以及 p型场效应晶体管，并且加热集成电路，使得沉积的材料与n型晶体管的多晶硅和p型晶体管的多晶硅反应以形成硅化物。形成在p型多晶硅上的硅化物沿着p型场效应晶体管的沟道的纵向施加压缩机械应力。通过该方法形成的半导体器件具有沿着PFET沟道的长度的压缩应力和沿着NFET沟道的长度的拉伸应力。

32. 发明授权

US06890808B2 Method and structure for improved MOSFETs using poly/silicide gate height control 失效
标题翻译：使用多晶硅/硅化物栅极高度控制的改进MOSFET的方法和结构
公开(公告)号：US06890808B2
公开(公告)日：2005-05-10
申请号：US10605135
申请日：2003-09-10
申请人： Dureseti Chidambarrao , Omer H. Dokumaci
发明人： Dureseti Chidambarrao , Omer H. Dokumaci
IPC分类号： H01L21/8238 , H01L21/84
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/84
摘要： A method for manufacturing an integrated circuit that has a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor. This method involves depositing oxide fill on the n-type transistor and the p-type transistor and chemical/mechanical polishing the deposited oxide fill such that a gate stack of the n-type transistor and a gate stack of the p-type transistor, which each have spacers which are surrounded with oxide. The method further involves etching a portion of the polysilicon from a gate of the p-type field effect transistor, depositing a low resistance material (e.g., Co, Ni, Ti, or other similar metals) on the n-type field effect transistor and the p-type field effect transistor, and heating the integrated circuit such that the deposited material reacts with the polysilicon of the n-type transistor and the polysilicon of the p-type transistor to form silicide. The silicide formed on the p-type polysilicon imposes compressive mechanical stresses along the longitudinal direction of the p-type field effect transistor. A semi-conductor device formed by this method has compressive stresses along the length of the PFET channel and tensile stresses along the length of the NFET channel.
摘要翻译：一种具有包括n型场效应晶体管和p型场效应晶体管的多个半导体器件的集成电路的制造方法。该方法包括在n型晶体管和p型晶体管上沉积氧化物填充物，并化学/机械抛光沉积的氧化物填充物，使得n型晶体管的栅极堆叠和p型晶体管的栅极堆叠，其中每个具有被氧化物包围的间隔物。该方法还包括从p型场效应晶体管的栅极蚀刻多晶硅的一部分，在n型场效应晶体管上沉积低电阻材料（例如，Co，Ni，Ti或其它类似的金属），以及 p型场效应晶体管，并且加热集成电路，使得沉积的材料与n型晶体管的多晶硅和p型晶体管的多晶硅反应以形成硅化物。在p型多晶硅上形成的硅化物沿p型场效应晶体管的纵向施加压缩机械应力。通过该方法形成的半导体器件具有沿PFET沟道长度的压缩应力和沿着NFET沟道长度的拉伸应力。

33. 发明授权

US06887751B2 MOSFET performance improvement using deformation in SOI structure 失效
公开(公告)号：US06887751B2
公开(公告)日：2005-05-03
申请号：US10605167
申请日：2003-09-12
申请人： Dureseti Chidambarrao , Omer H. Dokumaci
发明人： Dureseti Chidambarrao , Omer H. Dokumaci
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L21/8238
CPC分类号： H01L21/84 , H01L21/7624 , H01L27/1203 , H01L29/7849
摘要： A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor layer on a substrate. The first region of the substrate is expanded to push up the first portion of the semiconductor layer, thereby applying tensile stress to the first portion. The second region of the substrate is compressed to pull down the second portion of the semiconductor layer, thereby applying compressive stress to the second portion. An N type device is formed over the first portion of the semiconductor layer, and a P type device is formed over the second portion of the semiconductor layer.

34. 发明授权

US06709926B2 High performance logic and high density embedded dram with borderless contact and antispacer 失效
标题翻译：高性能逻辑和高密度嵌入式电脑，无边界接触和对抗
公开(公告)号：US06709926B2
公开(公告)日：2004-03-23
申请号：US10160540
申请日：2002-05-31
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
IPC分类号： H01L21336
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.
摘要翻译：集成电路包括具有以最小光刻特征尺寸分隔的阵列晶体管的存储单元，以及由扩散阻挡层封装的非硅化金属位线，而高性能逻辑晶体管可以形成在同一芯片上，而不会损害性能，包括有效沟道硅化触点低源极/漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅极电介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。该结构通过易平坦化的材料实现，并且使用平坦化为不同材料的结构的高度的类似掩模来去耦合逻辑晶体管中的衬底和栅极注入。

35. 发明授权

US08232153B2 Silicon device on Si:C-OI and SGOI and method of manufacture 有权
标题翻译： Si：C-OI和SGOI上的硅器件及其制造方法
公开(公告)号：US08232153B2
公开(公告)日：2012-07-31
申请号：US11757874
申请日：2007-06-04
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
IPC分类号： H01L21/337 , H01L21/8238 , H01L29/00
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译：提供半导体结构和制造方法。制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。在第一岛和第二岛上形成不同材料的层。科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

36. 发明授权

US07495291B2 Strained dislocation-free channels for CMOS and method of manufacture 有权
标题翻译：用于CMOS的应变无位错通道和制造方法
公开(公告)号：US07495291B2
公开(公告)日：2009-02-24
申请号：US11061445
申请日：2005-02-22
申请人： Dureseti Chidambarrao , Omer H. Dokumaci
发明人： Dureseti Chidambarrao , Omer H. Dokumaci
IPC分类号： H01L23/62
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/66621 , Y10S438/933
摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET channel and a Si:C layer is grown in the pFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component in an overlying grown epitaxial layer. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In a further implementation, the SiGe layer is grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.
摘要翻译：半导体器件及半导体器件的制造方法。半导体器件包括用于pFET和nFET的沟道。在nFET沟道的沟道中生长SiGe层，并且在pFET沟道中生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配，以在覆盖的生长的外延层中产生应力分量。在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。在另一实施方案中，SiGe层在nFET和pFET沟道中生长。在这种实现中，pFET通道中的应力水平应该大于3GPa。

37. 发明申请

US20080164532A1 EMBEDDED STRESSED NITRIDE LINERS FOR CMOS PERFORMANCE IMPROVEMENT 有权
标题翻译：用于CMOS性能改进的嵌入式应力氮化物线
公开(公告)号：US20080164532A1
公开(公告)日：2008-07-10
申请号：US12049450
申请日：2008-03-17
申请人： Dureseti Chidambarrao , Omer H. Dokumaci
发明人： Dureseti Chidambarrao , Omer H. Dokumaci
IPC分类号： H01L27/00
CPC分类号： H01L21/823807 , H01L21/28247 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.
摘要翻译：本发明提供了一种半导体器件，其包括位于衬底的台面部分上的栅极区域; 以及位于所述栅极区域上的氮化物衬垫和与所述栅极区域相邻的所述衬底的凹陷表面，所述氮化物衬垫向所述栅极区域下方的器件沟道施加压力。在器件通道上产生的应力是大约275MPa至大约450MPa的纵向应力。

38. 发明授权

US07374987B2 Stress inducing spacers 有权
标题翻译：应力诱导垫片
公开(公告)号：US07374987B2
公开(公告)日：2008-05-20
申请号：US10935136
申请日：2004-09-07
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Jack A. Mandelman , Xavier Baie
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Jack A. Mandelman , Xavier Baie
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/42316 , H01L29/7842 , H01L29/7843 , H01L29/808
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.
摘要翻译：在张力和/或压缩下的基底改善了在其中制造的器件的性能。可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。

39. 发明授权

US07144767B2 NFETs using gate induced stress modulation 失效
标题翻译：使用栅极诱导应力调制的NFET
公开(公告)号：US07144767B2
公开(公告)日：2006-12-05
申请号：US10667601
申请日：2003-09-23
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
IPC分类号： H01L21/8249
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828
摘要： A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor.
摘要翻译：一种用于制造集成电路的方法，该集成电路包括通过用掩模覆盖p型场效应晶体管的多个半导体器件，包括n型场效应晶体管和p型场效应晶体管，并且氧化栅极多晶硅的一部分的n型场效应晶体管，使得在n型场效应晶体管的沟道内形成拉伸机械应力。

40. 发明授权

US06974981B2 Isolation structures for imposing stress patterns 有权
标题翻译：施加应力模式的隔离结构
公开(公告)号：US06974981B2
公开(公告)日：2005-12-13
申请号：US10318600
申请日：2002-12-12
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Jack A. Mandelman
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Jack A. Mandelman
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L29/80 , H01L31/109 , H01L31/112 , H01L29/774
CPC分类号： H01L29/7846 , H01L21/76232 , H01L21/823807 , H01L21/823878 , H01L29/785
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.
摘要翻译：在张力和/或压缩下的基底改善了在其中制造的器件的性能。可以通过选择适当的STI填充材料将张力和/或压缩施加在基底上。 STI区域形成在衬底层中并且在相邻衬底区域上施加力。在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，实现了IC性能的提高。

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