专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20070057334A1 MOSFET WITH HIGH ANGLE SIDEWALL GATE AND CONTACTS FOR REDUCED MILLER CAPACITANCE 有权
标题翻译：具有高角度门窗的MOSFET和用于减少MILLER电容的触点
公开(公告)号：US20070057334A1
公开(公告)日：2007-03-15
申请号：US11162424
申请日：2005-09-09
申请人： Dureseti Chidambarrao , Lawrence Clevenger , Omer Dokumaci , Kaushik Kumar , Huilong Zhu
发明人： Dureseti Chidambarrao , Lawrence Clevenger , Omer Dokumaci , Kaushik Kumar , Huilong Zhu
IPC分类号： H01L29/94 , H01L21/3205
CPC分类号： H01L29/7836 , H01L21/26586 , H01L21/28518 , H01L21/76804 , H01L29/1083 , H01L29/665 , H01L29/6659
摘要： The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.
摘要翻译：本发明涉及一种FET器件，其具有带有倾斜侧壁的导电栅电极。具体来说，FET器件的侧壁从垂直方向偏移大于约0°且不大于约45°的偏移角。以这种方式，这种导电栅电极具有小于其基表面积的顶表面积。优选地，FET器件还包括源极/漏极金属触点，其特征还在于具有倾斜的侧壁，除了源极/漏极金属触点的偏移角度被布置成使得每个金属触点的顶表面积大于其基底表面区。与具有直壁栅电极和金属接触的常规FET器件相比，本发明的FET器件具有显着减小的栅极与漏极金属接触重叠电容，例如小于约0.07毫微微法每微米沟道宽度。

32. 发明授权

US07060539B2 Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby 失效
标题翻译：具有T形翅片的FinFET器件的制造方法和由此制造的器件
公开(公告)号：US07060539B2
公开(公告)日：2006-06-13
申请号：US10790550
申请日：2004-03-01
申请人： Dureseti Chidambarrao , Omer Dokumaci
发明人： Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L21/335 , H01L21/8232
CPC分类号： H01L29/7853 , H01L29/66795 , H01L29/7842
摘要： An FET device with a source island and a drain island is formed on a horizontal surface of a substrate comprising an insulating material. A channel structure formed over the horizontal surface of the substrate, which connects between the drain and the source, comprises a planar semiconductor channel fin formed above a vertical fin. The planar and vertical fins form a T-shaped cross-section. The bottom of the vertical fin contacts the horizontal surface of the substrate and the planar fin contacts the top of the vertical fin. A gate dielectric layer covers exposed surfaces of the channel structure. A gate electrode straddles the channel gate dielectric and the channel structure. A sacrificial layer, e.g. SiGe, deposited upon the substrate before forming the vertical fin, may be a semiconductor or dielectric material. The planar fin comprises a semiconductor material such as Si, SiGe or Ge.
摘要翻译：具有源极岛和漏极岛的FET器件形成在包括绝缘材料的衬底的水平表面上。在衬底的水平表面上形成的沟道结构，其连接在漏极和源极之间，包括形成在垂直鳍上方的平面半导体沟道鳍。平面和垂直翅片形成T形横截面。垂直翅片的底部接触衬底的水平表面，并且平面翅片接触垂直翅片的顶部。栅介质层覆盖通道结构的暴露表面。栅电极横跨沟道栅极电介质和沟道结构。牺牲层，例如在形成垂直翅片之前沉积在衬底上的SiGe可以是半导体或电介质材料。平面翅片包括诸如Si，SiGe或Ge的半导体材料。

33. 发明申请

US20060108651A1 Lowered Source/Drain Transistors 审中-公开
标题翻译：降低源/漏晶体管
公开(公告)号：US20060108651A1
公开(公告)日：2006-05-25
申请号：US10904660
申请日：2004-11-22
申请人： Huilong Zhu , Lawrence Clevenger , Omer Dokumaci , Oleg Gluschenkov , Kaushik Kumar , Carl Radens , Dureseti Chidambarrao
发明人： Huilong Zhu , Lawrence Clevenger , Omer Dokumaci , Oleg Gluschenkov , Kaushik Kumar , Carl Radens , Dureseti Chidambarrao
IPC分类号： H01L29/94
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/0843 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A novel transistor structure and method for fabrication the same. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. The method for fabricating the transistor structure starts out with a planar semiconductor layer and a gate stack on top of the semiconductor layer. Then, top regions of the semiconductor layer on opposing sides of the gate stack are removed. Then, regions beneath the removed regions are doped to form lowered S/D regions of the transistor structure
摘要翻译：一种新颖的晶体管结构及其制造方法。新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。用于制造晶体管结构的方法从在半导体层顶部的平面半导体层和栅叠层开始。然后，去除栅极堆叠的相对侧上的半导体层的顶部区域。然后，去除区域下方的区域被掺杂以形成晶体管结构的降低的S / D区域

34. 发明申请

US20060073649A1 Method for reduced N+ diffusion in strained Si on SiGe substrate 失效
标题翻译： SiGe衬底上应变Si中N +扩散减少的方法
公开(公告)号：US20060073649A1
公开(公告)日：2006-04-06
申请号：US11283882
申请日：2005-11-22
申请人： Dureseti Chidambarrao , Omer Dokumaci
发明人： Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/26513 , H01L29/1054 , H01L29/6656
摘要： Method for manufacturing a semiconductor device. The method includes forming source and drain extension regions in an upper surface of a SiGe-based substrate. The source and drain extension regions contain an N type impurity. Reducing vacancy concentration in the source and drain extension regions to decrease diffusion of the N type impurity contained in the first source and drain extension regions.
摘要翻译：半导体器件的制造方法该方法包括在基于SiGe的衬底的上表面中形成源极和漏极延伸区域。源极和漏极延伸区域包含N型杂质。降低源极和漏极延伸区域中的空位浓度，以减少第一源极和漏极延伸区域中包含的N型杂质的扩散。

35. 发明申请

US20050282325A1 Structure and method to improve channel mobility by gate electrode stress modification 审中-公开
公开(公告)号：US20050282325A1
公开(公告)日：2005-12-22
申请号：US11201163
申请日：2005-08-11
申请人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Oleg Gluschenkov
发明人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Oleg Gluschenkov
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

36. 发明申请

US20050280051A1 Isolation structures for imposing stress patterns 审中-公开
公开(公告)号：US20050280051A1
公开(公告)日：2005-12-22
申请号：US11200958
申请日：2005-08-10
申请人： Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Jack Mandelman
发明人： Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Jack Mandelman
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L29/80 , H01L31/109 , H01L31/112
CPC分类号： H01L29/7846 , H01L21/76232 , H01L21/823807 , H01L21/823878 , H01L29/785
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.

37. 发明申请

US20050258515A1 Embedded stressed nitride liners for CMOS performance improvement 有权
标题翻译：嵌入式应力氮化物衬垫可提高CMOS性能
公开(公告)号：US20050258515A1
公开(公告)日：2005-11-24
申请号：US10851828
申请日：2004-05-21
申请人： Dureseti Chidambarrao , Omer Dokumaci
发明人： Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L21/302 , H01L21/336 , H01L21/8238 , H01L23/58
CPC分类号： H01L21/823807 , H01L21/28247 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.
摘要翻译：本发明提供了一种半导体器件，其包括位于衬底的台面部分上的栅极区域; 以及位于所述栅极区域上的氮化物衬垫和与所述栅极区域相邻的所述衬底的凹陷表面，所述氮化物衬垫向所述栅极区域下方的器件沟道施加压力。在器件通道上产生的应力是大约275MPa至大约450MPa的纵向应力。

38. 发明申请

US20050104131A1 Silicon device on Si:C-OI and SGOI and method of manufacture 有权
标题翻译： Si：C-OI和SGOI上的硅器件及其制造方法
公开(公告)号：US20050104131A1
公开(公告)日：2005-05-19
申请号：US10715400
申请日：2003-11-19
申请人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
发明人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
IPC分类号： H01L21/82 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/24 , H01L29/808 , H01L29/10 , H01L27/01 , H01L29/00 , H01L31/036
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译：提供半导体结构和制造方法。制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。在第一岛和第二岛上形成不同材料的层。科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

39. 发明申请

US20050064687A1 SILICIDE PROXIMITY STRUCTURES FOR CMOS DEVICE PERFORMANCE IMPROVEMENTS 失效
标题翻译：用于CMOS器件性能改进的硅化物接近结构
公开(公告)号：US20050064687A1
公开(公告)日：2005-03-24
申请号：US10605310
申请日：2003-09-22
申请人： Dureseti Chidambarrao , Omer Dokumaci , Rajesh Rengarajan , An Steegen
发明人： Dureseti Chidambarrao , Omer Dokumaci , Rajesh Rengarajan , An Steegen
IPC分类号： H01L21/28 , H01L21/336 , H01L21/38 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/458 , H01L29/7842 , H01L29/7845 , H01L29/78654
摘要： A method for manufacturing an integrated circuit having a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor on a semiconductor wafer by creating a spacer having a first width for the n-type field effect transistor and creating a spacer having a second width for the p-type field effect transistor, the first width being greater than the second width and depositing silicide material on the semiconductor wafer such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor and compressive stresses are formed within a channel of the p-type field effect transistor.
摘要翻译：一种制造集成电路的方法，该集成电路具有在半导体晶片上具有n型场效应晶体管和p型场效应晶体管的多个半导体器件，该半导体器件具有用于n型场效应晶体管的具有第一宽度的间隔物，以及产生具有用于p型场效应晶体管的第二宽度的间隔物，第一宽度大于第二宽度，并且在半导体晶片上沉积硅化物材料，使得在n型场效应的沟道内形成拉伸机械应力在p型场效应晶体管的沟道内形成晶体管和压应力。

40. 发明申请

US20050003605A1 CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEFECTS 失效
标题翻译： CMOS性能增强使用本地化声音和扩展缺陷
公开(公告)号：US20050003605A1
公开(公告)日：2005-01-06
申请号：US10879550
申请日：2004-06-29
申请人： Omer Dokumaci , Dureseti Chidambarrao , Suryanarayan Hegde
发明人： Omer Dokumaci , Dureseti Chidambarrao , Suryanarayan Hegde
IPC分类号： H01L21/8238 , H03B1/00
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814
摘要： The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.
摘要翻译： CMOS电路的速度通过在NFET上施加纵向拉伸应力和PFET上的纵向压缩应力，通过将元素周期表第八列中的NFET离子的源和漏极注入氢中并将其植入到来自周期表第四和第六列的PFET离子的源极和漏极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式