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31. 发明授权

US08492213B2 Transistor and method for forming the same 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US08492213B2
公开(公告)日：2013-07-23
申请号：US13204319
申请日：2011-08-05
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/335 , H01L21/70
CPC分类号： H01L29/7833 , H01L29/045 , H01L29/0847 , H01L29/1054 , H01L29/66492 , H01L29/66545 , H01L29/66651 , H01L29/7848 , H01L29/7849
摘要： The invention discloses a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on a substrate; and grid electrodes, source cathode doped areas, drain doped areas, and side walls formed on two sides of the grid electrodes are arranged on the NMOS transistor and the PMOS transistor respectively. The device is characterized in that the side walls on the two sides of the grid electrode of the NMOS transistor possess tensile stress, and the side walls on the two sides of the grid electrode of the PMOS transistor possess compressive stress. The stress gives the side walls a greater role in adjusting the stress applied to channels and the source/drain areas, with the carrier mobility further enhanced and the performance of the device improved.
摘要翻译：本发明公开了一种半导体器件，其包括形成在衬底上的NMOS晶体管和PMOS晶体管; 并且分别在NMOS晶体管和PMOS晶体管上分别设置格栅电极，源极阴极掺杂区域，漏极掺杂区域和形成在栅电极两侧的侧壁。该器件的特征在于，NMOS晶体管的栅电极的两侧的侧壁具有拉伸应力，并且PMOS晶体管的栅电极的两侧上的侧壁具有压应力。应力使得侧壁在调节施加到通道和源极/漏极区域的应力方面发挥更大的作用，其中载流子迁移率进一步增强并且器件的性能得到改善。

32. 发明申请

US20130168746A1 SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US20130168746A1
公开(公告)日：2013-07-04
申请号：US13618004
申请日：2012-09-14
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： A semiconductor device manufacturing method includes providing a mask on a semiconductor member. The method further includes providing a dummy element to cover a portion of the mask that overlaps a first portion of the semiconductor member and to cover a second portion of the semiconductor member. The method further includes removing a third portion of the semiconductor member, which has not been covered by the mask or the dummy element. The method further includes providing a silicon compound that contacts the first portion of the semiconductor member. The method further includes removing the dummy element to expose and to remove the second portion of the semiconductor member. The method further includes forming a gate structure that overlaps the first portion of the semiconductor member. The first portion of the semiconductor member is used as a channel region and is supported by the silicon compound.
摘要翻译：半导体器件制造方法包括在半导体部件上设置掩模。该方法还包括提供虚拟元件以覆盖与半导体部件的第一部分重叠并覆盖半导体部件的第二部分的掩模的一部分。该方法还包括去除未被掩模或虚拟元件覆盖的半导体部件的第三部分。该方法还包括提供接触半导体部件的第一部分的硅化合物。该方法还包括去除虚设元件以暴露并移除半导体部件的第二部分。该方法还包括形成与半导体部件的第一部分重叠的栅极结构。半导体部件的第一部分用作沟道区域并由硅化合物支撑。

33. 发明授权

US08409883B2 Method for fabricating a phase change memory 有权
标题翻译：相变存储器的制造方法
公开(公告)号：US08409883B2
公开(公告)日：2013-04-02
申请号：US13157076
申请日：2011-06-09
申请人： Fumitake Mieno , Youfeng He
发明人： Fumitake Mieno , Youfeng He
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L27/15 , H01L27/24 , H01L45/1213 , H01L45/144
摘要： The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, peripheral shallow trench isolation (STI) units in the peripheral substrate, and MOS transistors on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, vertical LEDs on the on the N-type ion buried layer, storage shallow trench isolation (STI) units between the vertical LEDs, and phase change layers on the vertical LEDs and between the storage STI units. The storage STI units have thickness equal to thickness of the vertical LEDs. Each vertical LED comprises an N-type conductive region on the N-type ion buried layer, and a P-type conductive region on the N-type conductive region. The P-type conductive region contains SiGe. The peripheral STI units have thickness equal to thickness of the storage STI units. A top of P-type conductive region is flush with a top of the peripheral substrate. The P-type conductive region containing SiGe reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.
摘要翻译：本发明提供一种相变存储器和形成相变存储器的方法。相变存储器包括存储区域和外围电路区域。外围电路区域具有周边基板，外围基板中的外围浅沟槽隔离（STI）单元，以及外围基板上的MOS晶体管和周边STI单元之间的MOS晶体管。存储区具有存储基板，存储基板上的N型离子埋层，N型离子埋层上的垂直LED，垂直LED之间的存储浅沟槽隔离（STI）单元和相变层在垂直LED和存储STI单元之间。存储STI单元的厚度等于垂直LED的厚度。每个垂直LED包括在N型离子掩埋层上的N型导电区域和N型导电区域上的P型导电区域。 P型导电区域含有SiGe。外围STI单元的厚度等于存储STI单元的厚度。 P型导电区域的顶部与外围基板的顶部齐平。含有SiGe的P型导电区域降低了通过垂直LED的漏极电流，提高了垂直LED的电流效率。外围电路区域可以正常工作，而不会对相变存储器的性能产生不利影响。

34. 发明申请

US20110053349A1 APPLICATION OF MILLISECOND HEATING SOURCE FOR SURFACE TREATMENT 有权
标题翻译：用于表面处理的MILLISECOND加热源的应用
公开(公告)号：US20110053349A1
公开(公告)日：2011-03-03
申请号：US12842017
申请日：2010-07-22
申请人： DAVID GAO , Fumitake Mieno
发明人： DAVID GAO , Fumitake Mieno
IPC分类号： H01L21/322
CPC分类号： H01L21/268 , H01L21/02046 , H01L21/02057 , H01L21/02098 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848 , Y10S134/902
摘要： A method for fabricating semiconductor devices, e.g., strained silicon MOS device, includes providing a semiconductor substrate (e.g., silicon wafer) having a surface region, which has one or more contaminants and an overlying oxide layer. The one or more contaminants is at least a carbon species. The method also includes processing the surface region using at least a wet process to selectively remove the oxide layer and expose the surface region. The method further includes subjecting the surface region to a laser treatment process for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants provided on the surface region. The method also includes removing the laser treatment process to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second.
摘要翻译：制造半导体器件（例如应变硅MOS器件）的方法包括提供具有表面区域的半导体衬底（例如，硅晶片），该表面区域具有一个或多个污染物和上覆氧化物层。一种或多种污染物是至少一种碳类。该方法还包括使用至少湿法处理表面区域以选择性地去除氧化物层并暴露表面区域。该方法还包括使表面区域进行激光处理过程，持续时间小于1秒，以将表面区域的温度升高至大于1000摄氏度，以去除表面区域上提供的一种或多种污染物。该方法还包括去除激光处理过程，以在小于1秒的时间段内将温度降低至约300至约600摄氏度。

35. 发明授权

US07887884B2 Method for atomic layer deposition of materials using an atmospheric pressure for semiconductor devices 有权
标题翻译：用于半导体器件的大气压原子层沉积材料的方法
公开(公告)号：US07887884B2
公开(公告)日：2011-02-15
申请号：US11243735
申请日：2005-10-04
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： C23C16/00
CPC分类号： C23C16/403 , C23C16/45525 , C23C16/45551
摘要： A method for atomic layer deposition. The method includes providing a substrate having a surface region and exposing the surface region of the substrate to an atmospheric pressure. The method also maintains at least the substrate at about the atmospheric pressure and forms a film overlying the surface region using atomic layer deposition, while the substrate is maintained at about atmospheric pressure. Preferably, the film is grown at a rate of greater than about 1 nanometer per minute.
摘要翻译：一种原子层沉积的方法。该方法包括提供具有表面区域并将衬底的表面区域暴露于大气压的衬底。该方法还在大气压附近至少保持基板，并且使用原子层沉积形成覆盖表面区域的膜，同时将基板保持在大气压附近。优选地，膜以大于约1纳米每分钟的速率生长。

36. 发明申请

US20100001334A1 ATOMIC LAYER DEPOSITION EPITAXIAL SILICON GROWTH FOR TFT FLASH MEMORY CELL 有权
标题翻译：用于TFT闪存存储器的原子层沉积外延硅生长
公开(公告)号：US20100001334A1
公开(公告)日：2010-01-07
申请号：US12259128
申请日：2008-10-27
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L29/786 , H01L21/36 , H01L21/8232
CPC分类号： H01L21/02381 , H01L21/02488 , H01L21/02499 , H01L21/02532 , H01L21/0262 , H01L21/28273 , H01L27/11521 , H01L29/66825 , H01L29/78672
摘要： A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.
摘要翻译：提供了生长外延硅层的方法。该方法包括提供包含氧封端的硅表面的衬底，并在氧封端的硅表面上形成第一个氢封端的硅表面。此外，该方法包括通过原子层沉积（ALD）外延从由Ar流和闪光灯退火辅助的SiH 4热裂解基团连续形成在第一氢封端硅表面上的第二氢封端硅表面。第二个氢封端的硅表面能够连续地由Ar流和闪光灯退火辅助的SiH 4热裂解基团通过ALD外延添加一层或多层硅。在一个实施例中，该方法被应用于制造具有能够进行三维集成的薄膜晶体管（TFT）浮动栅极存储单元结构的器件。

37. 发明申请

US20100001282A1 TFT FLOATING GATE MEMORY CELL STRUCTURES 有权
标题翻译： TFT浮动栅格存储器单元结构
公开(公告)号：US20100001282A1
公开(公告)日：2010-01-07
申请号：US12259165
申请日：2008-10-27
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L29/788 , H01L21/84
CPC分类号： H01L29/788 , H01L29/66757 , H01L29/66825 , H01L29/7881
摘要： A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface and a floating gate on the P− polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P+ polysilicon layer overlying the upper oxide block layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.
摘要翻译：提供一种具有薄膜晶体管（TFT）浮动栅极存储单元结构的器件。该器件包括衬底，衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域。介电层与第一表面相关联。所述一个或多个源区或漏区中的每一个包括在第一导电层上的扩散阻挡层上的N +多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。另外，该器件包括覆盖共面表面的P-多晶硅层和P-多晶硅层上的浮置栅极。浮栅是由底部氧化物隧道层和上部氧化物阻挡层夹在中间的低压CVD沉积硅层。此外，该器件包括至少一个由覆盖在上氧化物块层上的P +多晶硅层制成的控制栅极。提供了制造相同存储单元结构的方法，并且可以重复三维地集成结构。

38. 发明授权

US5082695A Method of fabricating an X-ray exposure mask 失效
标题翻译：制造X射线曝光掩模的方法
公开(公告)号：US5082695A
公开(公告)日：1992-01-21
申请号：US314794
申请日：1989-02-24
申请人： Masao Yamada , Masafumi Nakaishi , Kenji Nakagawa , Yuji Furumura , Takashi Eshita , Fumitake Mieno
发明人： Masao Yamada , Masafumi Nakaishi , Kenji Nakagawa , Yuji Furumura , Takashi Eshita , Fumitake Mieno
IPC分类号： G03F1/22
CPC分类号： G03F1/22
摘要： A method of fabricating an X-ray exposure mask including the steps of forming a .beta.-SiC membrane by chemcial vapor deposition and simultaneously doping the membrane with at least one of phosphorous, boron, nitrogen and oxygen.

39. 发明授权

US09263566B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09263566B2
公开(公告)日：2016-02-16
申请号：US13351139
申请日：2012-01-16
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/28 , H01L23/498 , H01L29/43 , H01L29/778 , H01L29/66 , H01L29/10 , H01L29/49 , H01L29/165
CPC分类号： H01L29/4983 , H01L21/28255 , H01L29/1054 , H01L29/165 , H01L29/66545 , H01L29/66651 , H01L29/7781
摘要： The present invention relates to a semiconductor device and its manufacturing method. The semiconductor device comprises: a gate structure located on a substrate, Ge-containing semiconductor layers located on the opposite sides of the gate structure, a doped semiconductor layer epitaxially grown between the Ge-containing semiconductor layers, the bottom surfaces of the Ge-containing semiconductor layers located on the same horizontal plane as that of the epitaxial semiconductor layer. The epitaxial semiconductor layer is used as a channel region, and the Ge-containing semiconductor layers are used as source/drain extension regions.
摘要翻译：本发明涉及一种半导体器件及其制造方法。半导体器件包括：位于衬底上的栅极结构，位于栅极结构的相对侧上的含锗半导体层，外延生长在含锗半导体层之间的掺杂半导体层，含Ge的半导体层的底表面位于与外延半导体层相同的水平面上的半导体层。使用外延半导体层作为沟道区，将含Ge半导体层用作源/漏延伸区。

40. 发明授权

US08420511B2 Transistor and method for forming the same 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US08420511B2
公开(公告)日：2013-04-16
申请号：US13196671
申请日：2011-08-02
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/8238 , H01L21/322 , H01L29/78
CPC分类号： H01L29/045 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L29/1054 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The invention provides a method for forming a transistor, which includes: providing a substrate, a semiconductor layer being formed on the substrate; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer; removing the dummy gate structure for forming an opening in the interlayer dielectric layer; non-crystallizing the semiconductor layer exposed in the opening for forming a channel layer; annealing the channel layer so that the channel layer and the substrate have same crystal orientation; and forming a metal gate structure in the opening, the metal gate being formed on the channel layer. Saturation current of the transistor is raised, and the performance of a semiconductor device is promoted.
摘要翻译：本发明提供了一种形成晶体管的方法，其包括：提供衬底，在衬底上形成半导体层; 在半导体层上形成虚拟栅极结构; 在衬底和半导体层以及虚拟栅极结构的相对侧形成源区和漏区; 在所述半导体层上形成层间绝缘层; 去除用于在层间电介质层中形成开口的伪栅极结构; 在形成沟道层的开口中暴露的半导体层不结晶; 使沟道层退火，使得沟道层和衬底具有相同的晶体取向; 以及在所述开口中形成金属栅极结构，所述金属栅极形成在所述沟道层上。提高晶体管的饱和电流，提高半导体器件的性能。

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