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31. 发明授权

US07884473B2 Method and structure for increased wire bond density in packages for semiconductor chips 有权
标题翻译：用于半导体芯片的封装中增加引线键合密度的方法和结构
公开(公告)号：US07884473B2
公开(公告)日：2011-02-08
申请号：US11850283
申请日：2007-09-05
申请人： Hsien-Wei Chen , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Shih-Hsun Hsu
IPC分类号： H01L23/49
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/32145 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/48844 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/49175 , H01L2224/49431 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/20751 , H01L2924/00 , H01L2224/48824 , H01L2224/48744 , H01L2224/45099 , H01L2924/00015 , H01L2924/00012
摘要： A semiconductor package provides an IC chip on at least one package substrate and including signal bond pads, ground bond pads and power bond pads. The package substrate includes signal contact pads, ground contact pads and power contact pads which are respectively coupled to signal bond pads, ground bond pads and power bond pads formed on the IC chip. The contact pads are coupled to the associated bond pads by a bonding wire. The bonding wires that connect the power and ground pads have a thickness that is greater than the thickness of the bonding wires that couple the signal pads. The various bond pads on the IC chip may be staggered to provide for enhanced compactness and integration. The package substrates may be a plurality of stacked package substrates.
摘要翻译：半导体封装在至少一个封装衬底上提供IC芯片，并且包括信号焊盘，接地焊盘和电源焊盘。封装衬底包括信号接触焊盘，接地焊盘和功率接触焊盘，其分别耦合到形成在IC芯片上的信号焊盘，接地焊盘和功率接合焊盘。接触垫通过接合线耦合到相关联的接合焊盘。连接电源和接地焊盘的接合线的厚度大于连接信号焊盘的接合线的厚度。 IC芯片上的各种接合焊盘可以交错以提供增强的紧凑性和集成度。封装衬底可以是多个堆叠的封装衬底。

32. 发明授权

US07834351B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07834351B2
公开(公告)日：2010-11-16
申请号：US12426995
申请日：2009-04-21
申请人： Hsien-Wei Chen , Shih-Hsun Hsu , Hsueh-Chung Chen
发明人： Hsien-Wei Chen , Shih-Hsun Hsu , Hsueh-Chung Chen
IPC分类号： H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.
摘要翻译：公开了一种半导体器件。该器件包括衬底和覆盖衬底的第一布线层。第一布线层包括由第一密封环包围的第一布线区域。第一密封环包括由嵌入在第一密封环中的第一介电层隔离的第一监测电路。第一监视器电路响应于在第三电介质层中发生预定量的变形。

33. 发明申请

US20080277659A1 Test structure for semiconductor chip 审中-公开
标题翻译：半导体芯片测试结构
公开(公告)号：US20080277659A1
公开(公告)日：2008-11-13
申请号：US11801529
申请日：2007-05-10
申请人： Shih-Hsun Hsu , Hsien-Wei Chen , Anbiarshy N.F. Wu
发明人： Shih-Hsun Hsu , Hsien-Wei Chen , Anbiarshy N.F. Wu
IPC分类号： H01L23/544
CPC分类号： H01L27/0203 , H01L22/34 , H01L23/585 , H01L2223/5446 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A test structure for use in a semiconductor chip. In a preferred embodiment, a number of die are formed in an array on a semiconductor wafer substrate. Each die includes an active area defined by a seal ring and is separated from those adjacent to it by a thin scribe line. In addition to the operational structures formed in the active area of each die, one or more test structures are formed. In a preferred embodiment, these test structures are formed into one or more PCM (process control monitor) test pattern layout areas that are positioned near the seal ring and outside of the operational bond pads. Some or all of individual pads in the PCM test pattern layout area may then be connected to corresponding features on adjacent dice, and in some applications enable the simultaneous performance of WAT (wafer acceptance test) and CP (circuit probe) testing.
摘要翻译：用于半导体芯片的测试结构。在优选实施例中，在半导体晶片衬底上以阵列形式形成多个管芯。每个模具包括由密封环限定的有效区域，并通过薄的划线与其相邻的区域分开。除了在每个管芯的有源区域中形成的操作结构之外，还形成一个或多个测试结构。在优选实施例中，这些测试结构被形成为位于密封环附近和操作接合焊盘外部的一个或多个PCM（过程控制监视器）测试图案布局区域。 PCM测试图案布局区域中的单个焊盘中的一些或全部可以连接到相邻裸片上的相应特征，并且在某些应用中，能够同时执行WAT（晶片验收测试）和CP（电路探针）测试。

34. 发明授权

US08072076B2 Bond pad structures and integrated circuit chip having the same 有权
标题翻译：焊盘结构和集成电路芯片具有相同的功能
公开(公告)号：US08072076B2
公开(公告)日：2011-12-06
申请号：US11545579
申请日：2006-10-11
申请人： Shih-Hsun Hsu , Shih-Puu Jeng , Shang-Yun Hou , Hsien-Wei Chen
发明人： Shih-Hsun Hsu , Shih-Puu Jeng , Shang-Yun Hou , Hsien-Wei Chen
IPC分类号： H01L23/48 , H01L23/544 , H01L29/41
CPC分类号： H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05552 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/05042 , H01L2924/14 , H01L2924/00014
摘要： Bonding pad structures and integrated circuits having the same are provided. An exemplary embodiment of a bond pad structure comprises a bond pad layer. A passivation layer partially covers the bond pad layer from edges thereof and exposes a bonding surface, wherein the passivation layer is formed with a recess on at least one edge of the bonding surface to thereby define a probe needle contact area for probe needle testing and a wire bonding area for wire bonding on the bonding surface, and the probe needle contact area and the wire bonding area have a non-overlapping relationship.
摘要翻译：提供接合焊盘结构和具有该结合焊盘结构的集成电路。接合焊盘结构的示例性实施例包括接合焊盘层。钝化层从其边缘部分地覆盖接合焊盘层并暴露接合表面，其中钝化层在接合表面的至少一个边缘上形成有凹陷，从而限定用于探针针测试的探针接触面积接合面上引线接合的引线接合区域，探针针接触面积和引线接合区域具有不重叠的关系。

35. 发明授权

US07692274B2 Reinforced semiconductor structures 失效
标题翻译：加强半导体结构
公开(公告)号：US07692274B2
公开(公告)日：2010-04-06
申请号：US11649244
申请日：2007-01-04
申请人： Hsien-Wei Chen , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Shih-Hsun Hsu
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L21/78 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Reinforced semiconductor structures are provided. An exemplary embodiment of a reinforced semiconductor structure comprises a semiconductor wafer comprising a plurality of dielectric layers formed thereon. At least one scribe line region is defined over the semiconductor wafer, separating the semiconductor wafer with at least two active regions thereover. A plurality of first non-dielectric pillars are formed in the topmost layer of the dielectric layers in the scribe line region and surround the test pad along a periphery. A plurality of second non-dielectric pillars and first vias are formed in a first low-k dielectric layer underlying the topmost low-k layer in the scribe line region, wherein the second non-dielectric pillars electrically connect the first non-dielectric pillars by the first vias, respectively.
摘要翻译：提供了增强的半导体结构。增强半导体结构的示例性实施例包括其上形成有多个电介质层的半导体晶片。在半导体晶片上限定至少一个划线区域，其中半导体晶片与其上的至少两个有源区域分开。在划线区域的电介质层的最上层形成有多个第一非绝缘柱，并沿着周边包围测试垫。多个第二非介电柱和第一通孔形成在划线区域中的最低低k层下面的第一低k电介质层中，其中第二非介电柱将第一非介电柱电连接第一非介电柱第一个通孔。

36. 发明申请

US20080277806A1 SEMICONDUCTOR WAFER WITH ASSISTING DICING STRUCTURE AND DICING METHOD THEREOF 有权
标题翻译：具有辅助结构的半导体晶片及其定义方法
公开(公告)号：US20080277806A1
公开(公告)日：2008-11-13
申请号：US11745595
申请日：2007-05-08
申请人： Hsien-Wei Chen , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Shih-Hsun Hsu
IPC分类号： H01L23/544 , H01L21/00
CPC分类号： H01L21/78 , B28D5/022 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed.
摘要翻译：具有辅助切割结构的半导体晶片。晶片包括具有前表面和后表面的基板。衬底的前表面包括由至少一个切割通道分开的至少两个器件区域。衬底的后表面包括形成在其中并与切割通道基本对齐的至少一个预切割沟槽。还公开了一种用于切割半导体晶片的方法。

37. 发明申请

US20080164468A1 Reinforced semiconductor structures 失效
标题翻译：加强半导体结构
公开(公告)号：US20080164468A1
公开(公告)日：2008-07-10
申请号：US11649244
申请日：2007-01-04
申请人： Hsien-Wei Chen , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Shih-Hsun Hsu
IPC分类号： H01L23/58
CPC分类号： H01L23/585 , H01L21/78 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Reinforced semiconductor structures are provided. An exemplary embodiment of a reinforced semiconductor structure comprises a semiconductor wafer comprising a plurality of dielectric layers formed thereon. At least one scribe line region is defined over the semiconductor wafer, separating the semiconductor wafer with at least two active regions thereover. A plurality of first non-dielectric pillars are formed in the topmost layer of the dielectric layers in the scribe line region and surround the test pad along a periphery. A plurality of second non-dielectric pillars and first vias are formed in a first low-k dielectric layer underlying the topmost low-k layer in the scribe line region, wherein the second non-dielectric pillars electrically connect the first non-dielectric pillars by the first vias, respectively.
摘要翻译：提供了增强的半导体结构。增强半导体结构的示例性实施例包括其上形成有多个电介质层的半导体晶片。在半导体晶片上限定至少一个划线区域，其中半导体晶片与其上的至少两个有源区域分开。在划线区域的电介质层的最上层形成有多个第一非绝缘柱，并沿着周边包围测试垫。多个第二非介电柱和第一通孔形成在划线区域中的最低低k层下面的第一低k电介质层中，其中第二非介电柱将第一非介电柱电连接第一非介电柱第一个通孔。

38. 发明授权

US06660627B2 Method for planarization of wafers with high selectivities 有权
标题翻译：具有高选择性的晶片平面化方法
公开(公告)号：US06660627B2
公开(公告)日：2003-12-09
申请号：US10063133
申请日：2002-03-25
申请人： Shao-Chung Hu , Hsueh-Chung Chen , Shih-Hsun Hsu , Chia-Lin Hsu
发明人： Shao-Chung Hu , Hsueh-Chung Chen , Shih-Hsun Hsu , Chia-Lin Hsu
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/31051
摘要： A method for planarization of a semiconductor wafer with a high selectivity is describe. The semiconductor wafer has a hard mask, a stop layer disposed on the hard mask, and a barrier layer disposed on the stop layer. The method includes performing a chemical mechanical polishing (CMP) process on the barrier layer so as to expose the stop layer, and removing the stop layer. The polishing selectivity of the barrier layer relative to the stop layer is greater than 50. Since the material of stop layer is different from the material of barrier layer, the high selectivity is easily achieved. Thus, the surface of semiconductor wafer can be highly planarized.
摘要翻译：描述了一种以高选择性平坦化半导体晶片的方法。半导体晶片具有硬掩模，设置在硬掩模上的阻挡层和设置在阻挡层上的阻挡层。该方法包括在阻挡层上进行化学机械抛光（CMP）处理，以露出停止层，并除去停止层。阻挡层相对于停止层的抛光选择性大于50.由于阻挡层的材料与阻挡层的材料不同，因此容易实现高选择性。因此，半导体晶片的表面可以被高度平坦化。

39. 发明授权

US06797190B2 Wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same 有权
标题翻译：用于化学机械抛光装置的晶片载体组件和使用其的抛光方法
公开(公告)号：US06797190B2
公开(公告)日：2004-09-28
申请号：US10383983
申请日：2003-03-06
申请人： Chia-Lin Hsu , Art Yu , Shih-Hsun Hsu , Hsueh-Chung Chen
发明人： Chia-Lin Hsu , Art Yu , Shih-Hsun Hsu , Hsueh-Chung Chen
IPC分类号： B24D1100
CPC分类号： B24B37/30
摘要： A wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same are provided. The present wafer carrier assembly comprises a first plate, a second plate and a flexible membrane. The first plate has a plurality of protrusions formed on a bottom surface thereof and the second plate has a plurality of apertures passing through. Each of the protrusions is matched with one of the apertures to enable the first plate and the second plate to detachably combine together. The flexible membrane is positioned under the second plate and contacts it. A surface of the flexible membrane opposite to the surface of the flexible membrane contacting the second plate provides a wafer-receiving surface.
摘要翻译：提供了一种用于化学机械抛光装置的晶片载体组件和使用其的抛光方法。本晶片载体组件包括第一板，第二板和柔性膜。第一板具有在其底表面上形成的多个突起，并且第二板具有穿过的多个孔。每个突起与其中一个孔匹配，以使得第一板和第二板能够可拆卸地组合在一起。柔性膜定位在第二板下方并与其接触。与柔性膜的与第二板接触的表面相对的柔性膜的表面提供了晶片接收表面。

40. 发明授权

US06709544B2 Chemical mechanical polishing equipment 失效
标题翻译：化学机械抛光设备
公开(公告)号：US06709544B2
公开(公告)日：2004-03-23
申请号：US10064526
申请日：2002-07-24
申请人： Shao-Chung Hu , Chia-Lin Hsu , Hsueh-Chung Chen , Shih-Hsun Hsu
发明人： Shao-Chung Hu , Chia-Lin Hsu , Hsueh-Chung Chen , Shih-Hsun Hsu
IPC分类号： B24B700
CPC分类号： B24B37/20 , B24B37/042
摘要： The present invention related to a CMP equipment, compatible with the existing manufacture processes. The CMP equipment of the present invention employs strip polishing platens that can be smaller than the wafer size, so that the layout is compact and the space is effectively utilized, leading to high throughput and efficient production management. The present invention provides a CMP equipment that offers greater flexibility in performing CMP for different fabrication processes through the choices of various polishing pads and/or polishing slurry.
摘要翻译：本发明涉及与现有制造工艺兼容的CMP设备。本发明的CMP设备采用可以比晶片尺寸小的带状抛光压板，使得布局紧凑并且有效地利用空间，导致高产量和高效的生产管理。本发明提供一种CMP设备，其通过选择各种抛光垫和/或抛光浆料，为不同的制造工艺执行CMP提供更大的灵活性。

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