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31. 发明授权

US08178407B2 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US08178407B2
公开(公告)日：2012-05-15
申请号：US12561395
申请日：2009-09-17
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

32. 发明授权

US07817472B2 Operating method of memory device 有权
标题翻译：存储器件的操作方法
公开(公告)号：US07817472B2
公开(公告)日：2010-10-19
申请号：US12169155
申请日：2008-07-08
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/14
摘要： An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array.
摘要翻译：提供了一种存储器阵列的操作方法。操作方法包括执行编程操作。通过将第一电压施加到存储器阵列的位线并将第二电压施加到存储器阵列的多个字线来执行编程操作，以同时对存储器阵列中的多个选择的存储器单元进行编程。

33. 发明授权

US07787294B2 Operating method of memory 有权
标题翻译：记忆的操作方法
公开(公告)号：US07787294B2
公开(公告)日：2010-08-31
申请号：US12031189
申请日：2008-02-14
申请人： Ming-Chang Kuo , Ming-Hsiu Lee
发明人： Ming-Chang Kuo , Ming-Hsiu Lee
IPC分类号： G11C16/04
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0491
摘要： An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state.
摘要翻译：提供了一种存储器的操作方法。存储器包括由多个存储单元，多个位线和多个字线组成的存储单元阵列。在编程存储器期间，选择一列存储单元。在对应于所选列的存储单元的第一源极/漏极区域和相邻的两个位线的位线之间分别产生电压差，偏置分别施加到与每个存储单元的控制栅极相对应的字线在所选择的列中，以允许存储器单元的数据位处于多个预定编程状态，并且在相邻列中的每个存储器单元的不可用位与所选择的列共享与不可用状态相同的位线。

34. 发明申请

US20100091558A1 Dielectric-Sandwiched Pillar Memory Device 有权
标题翻译：介质三通支柱存储器件
公开(公告)号：US20100091558A1
公开(公告)日：2010-04-15
申请号：US12249178
申请日：2008-10-10
申请人： Ming-Hsiu Lee , Chieh-Fang Chen
发明人： Ming-Hsiu Lee , Chieh-Fang Chen
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C5/063 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C2213/34 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A memory device includes bottom and top electrode structures and a memory cell therebetween. The memory cell comprises bottom and top memory elements and a dielectric element therebetween. A lower resistance conduction path is formed through the dielectric element. The dielectric element may have an outer edge and a central portion, the outer edge being thicker than the central portion. To make a memory device, an electrical pulse is applied through the memory cell to form a conduction path through the dielectric element. A passivation element may be formed by oxidizing the outer surface of the memory cell which may also enlarge the outer edge of the dielectric element.
摘要翻译：存储器件包括底部和顶部电极结构以及它们之间的存储单元。存储单元包括底部和顶部存储器元件以及它们之间的介电元件。通过介电元件形成较低的电阻传导路径。电介质元件可以具有外边缘和中心部分，外边缘比中心部分厚。为了制造存储器件，通过存储器单元施加电脉冲以形成穿过介质元件的传导路径。可以通过氧化存储单元的外表面来形成钝化元件，该外表面也可以增大电介质元件的外边缘。

35. 发明申请

US20090207658A1 OPERATING METHOD OF MEMORY DEVICE 有权
标题翻译：存储器件的操作方法
公开(公告)号：US20090207658A1
公开(公告)日：2009-08-20
申请号：US12169155
申请日：2008-07-08
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-I Wu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0416 , G11C16/10 , G11C16/14
摘要： An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array
摘要翻译：提供了一种存储器阵列的操作方法。操作方法包括执行编程操作。通过将第一电压施加到存储器阵列的位线并将第二电压施加到存储器阵列的多个字线来执行编程操作，以同时编程存储器阵列中的多个选择的存储器单元

36. 发明申请

US20090207656A1 OPERATING METHOD OF MEMORY 有权
标题翻译：存储器的操作方法
公开(公告)号：US20090207656A1
公开(公告)日：2009-08-20
申请号：US12031189
申请日：2008-02-14
申请人： Ming-Chang Kuo , Ming-Hsiu Lee
发明人： Ming-Chang Kuo , Ming-Hsiu Lee
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0491
摘要： An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state.
摘要翻译：提供了一种存储器的操作方法。存储器包括由多个存储单元，多个位线和多个字线组成的存储单元阵列。在编程存储器期间，选择一列存储单元。在对应于所选列的存储单元的第一源极/漏极区域和相邻的两个位线的位线之间分别产生电压差，偏置分别施加到与每个存储单元的控制栅极相对应的字线在所选择的列中，以允许存储器单元的数据位处于多个预定编程状态，并且在相邻列中的每个存储器单元的不可用位与所选择的列共享与不可用状态相同的位线。

37. 发明申请

US20090101966A1 Method of identifying logical information in a programming and erasing cell by on-side reading scheme 有权
公开(公告)号：US20090101966A1
公开(公告)日：2009-04-23
申请号：US12314881
申请日：2008-12-18
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： H01L29/792
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

38. 发明申请

US20080084762A1 Method of identifying logical information in a programming and erasing cell by on-side reading scheme 有权
标题翻译：通过旁路读取方案识别编程和擦除单元中的逻辑信息的方法
公开(公告)号：US20080084762A1
公开(公告)日：2008-04-10
申请号：US11601710
申请日：2006-11-20
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.
摘要翻译：公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

39. 发明申请

US20080023699A1 A TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING 审中-公开
标题翻译：用于检测半导体加工过程中的充电效应的测试结构和方法
公开(公告)号：US20080023699A1
公开(公告)日：2008-01-31
申请号：US11460209
申请日：2006-07-26
申请人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L2224/73204 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
摘要翻译：半导体工艺测试结构包括电极，电荷俘获层和扩散区域。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

40. 发明申请

US20070285976A1 Intergrated circuit having a precharging circuit 有权
标题翻译：具有预充电电路的集成电路
公开(公告)号：US20070285976A1
公开(公告)日：2007-12-13
申请号：US11450605
申请日：2006-06-09
申请人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
发明人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0071 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A memory includes a phase change element having a first side and a second side and a first line coupled to the first side of the element. The memory includes an access device coupled to the second side of the element and a second line coupled to the access device for controlling the access device. The memory includes a circuit for precharging the first line to a first voltage and for applying a voltage pulse to the second line such that a current pulse is generated through the access device to the element to program the element to a selected one of more than two states. The voltage pulse has an amplitude based on the selected state.
摘要翻译：存储器包括具有第一侧和第二侧以及耦合到元件的第一侧的第一线的相变元件。存储器包括耦合到元件的第二侧的访问设备和耦合到访问设备的用于控制访问设备的第二行。存储器包括用于将第一线路预充电到第一电压并且用于将电压脉冲施加到第二线路的电路，使得通过该接入装置向该元件生成电流脉冲以将该元件编程为多于两个中的所选择的一个状态。电压脉冲具有基于选择状态的幅度。

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