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31. 发明申请

US20060043472A1 High density access transistor having increased channel width and methods of fabricating such devices 有权
标题翻译：具有增加的通道宽度的高密度存取晶体管和制造这种器件的方法
公开(公告)号：US20060043472A1
公开(公告)日：2006-03-02
申请号：US10925339
申请日：2004-08-24
申请人： Hongmei Wang , Chandra Mouli , Luan Tran
发明人： Hongmei Wang , Chandra Mouli , Luan Tran
IPC分类号： H01L29/94
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/10891 , H01L27/1203 , H01L29/41758 , H01L29/7841 , H01L29/785 , H01L29/7854 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to from word lines that intersect the active area lines at the angled segments.
摘要翻译：具有减小的单元尺寸并且具有增加的沟道宽度的晶体管的存储器件。更具体地，在衬底中形成支柱，使得侧壁被暴露。支柱的侧壁和柱的顶表面被栅极氧化物和多晶硅层覆盖以形成通过柱的通道。通过通道的电流通道大约等于柱的高度加上柱的宽度的两倍。支柱被图案化以形成具有成角度段的非线性有源面积线。多晶硅层被图案化成与成角度段的有源区域线相交的字线。

32. 发明申请

US20050193245A1 Internet protocol based disaster recovery of a server 有权
标题翻译：基于Internet协议的服务器的灾难恢复
公开(公告)号：US20050193245A1
公开(公告)日：2005-09-01
申请号：US10771591
申请日：2004-02-04
申请人： John Hayden , Hongmei Wang , Frederic Corniquet , Philippe Armangau , Pascal Donette , Aju John
发明人： John Hayden , Hongmei Wang , Frederic Corniquet , Philippe Armangau , Pascal Donette , Aju John
IPC分类号： G06F11/00
CPC分类号： G06F11/2069 , G06F11/2071 , G06F11/2097
摘要： For disaster recovery of a file server at an active site, the files that define the user environment of the file server are replicated to a virtual server at a disaster recovery site. To switch over user access from the active site to the disaster recovery site, the disaster recovery system determines whether there are sufficient network interfaces and file system mounts at the disaster recovery site. If so, the required resources are reserved, and user access is switched over. If not, an operator is given a list of missing resources or discrepancies, and a choice of termination or forced failover. Interruptions during the failover can be avoided by maintaining a copy of user mappings and a copy of session information at the disaster recovery site, and keeping alive client-server connections and re-directing client requests from the active site to the disaster recovery site.
摘要翻译：对于活动站点的文件服务器的灾难恢复，定义文件服务器的用户环境的文件将复制到灾难恢复站点的虚拟服务器。为了将用户访问从活动站点切换到灾难恢复站点，灾难恢复系统确定灾难恢复站点是否有足够的网络接口和文件系统装载。如果是这样，所需的资源被保留，并且用户访问被切换。如果没有，则给予运营商缺少资源或差异的列表，以及终止或强制故障转移的选择。可以通过在灾难恢复站点维护用户映射副本和会话信息的副本以及保持活动的客户端 - 服务器连接并将客户端请求从活动站点重定向到灾难恢复站点来避免故障转移期间的中断。

33. 发明授权

US06812103B2 Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects 有权
标题翻译：在MOSFET中制造电介质塞以抑制短沟道效应的方法
公开(公告)号：US06812103B2
公开(公告)日：2004-11-02
申请号：US10175774
申请日：2002-06-20
申请人： Hongmei Wang , Zhongze Wang
发明人： Hongmei Wang , Zhongze Wang
IPC分类号： H01L21336
CPC分类号： H01L29/66628 , H01L29/0649 , H01L29/0653 , H01L29/66636
摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.
摘要翻译：本发明提供了一种制造MOSFET中的电介质塞的技术。通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及源极之间的沟道区域和漏区。

34. 发明申请

US20130049096A1 METHODS AND APPARATUSES INCLUDING STRINGS OF MEMORY CELLS FORMED ALONG LEVELS OF SEMICONDUCTOR MATERIAL 有权
公开(公告)号：US20130049096A1
公开(公告)日：2013-02-28
申请号：US13222602
申请日：2011-08-31
申请人： Hongmei Wang
发明人： Hongmei Wang
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/16 , H01L29/7889 , H01L29/7926
摘要： Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed.

35. 发明申请

US20090176338A1 FULLY-DEPLETED (FD)(SOI) MOSFET ACCESS TRANSISTOR AND METHOD OF FABRICATION 有权
标题翻译：全掩模（FD）（SOI）MOSFET访问晶体管和制造方法
公开(公告)号：US20090176338A1
公开(公告)日：2009-07-09
申请号：US12401555
申请日：2009-03-10
申请人： Hongmei Wang , John K. Zahurak
发明人： Hongmei Wang , John K. Zahurak
IPC分类号： H01L21/84
CPC分类号： H01L29/4908 , H01L21/84 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1203 , H01L29/78621
摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.
摘要翻译：公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

36. 发明授权

US07189606B2 Method of forming fully-depleted (FD) SOI MOSFET access transistor 有权
标题翻译：形成全耗尽（FD）SOI MOSFET存取晶体管的方法
公开(公告)号：US07189606B2
公开(公告)日：2007-03-13
申请号：US10161615
申请日：2002-06-05
申请人： Hongmei Wang , John K. Zahurak
发明人： Hongmei Wang , John K. Zahurak
IPC分类号： H01L21/8238
CPC分类号： H01L29/4908 , H01L21/84 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1203 , H01L29/78621
摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.
摘要翻译：公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

37. 发明申请

US20060292838A1 Ion implanting methods 有权
标题翻译：离子注入方法
公开(公告)号：US20060292838A1
公开(公告)日：2006-12-28
申请号：US11168893
申请日：2005-06-28
申请人： Randall Culver , Terrence McDaniel , Hongmei Wang , James Dale , Richard Lane , Fred Fishburn
发明人： Randall Culver , Terrence McDaniel , Hongmei Wang , James Dale , Richard Lane , Fred Fishburn
IPC分类号： H01L21/22 , H01L21/31
CPC分类号： H01L21/26586 , H01L21/266
摘要： An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally pulled away from one another with a patterned photoresist layer received over the features and which has an opening therein received intermediate the pair of spaced features. While such spaced features are laterally pulled, a species is ion implanted into substrate material which is received lower than the pair of spaced features. After the ion implanting, the patterned photoresist layer is removed from the substrate. Other aspects and implementations are contemplated.
摘要翻译：离子注入方法包括形成从衬底向外突出的一对间隔且相邻的特征。所述一对间隔特征中的至少最外部的部分被横向地拉离彼此，图案化的光致抗蚀剂层被接收在特征上，并且其中具有开口，其中接收有一对隔开的特征。虽然这种间隔的特征被横向拉伸，但是一种物质被离子注入到被接收低于该对间隔特征的基底材料中。在离子注入之后，从衬底去除图案化的光致抗蚀剂层。考虑了其他方面和实现。

38. 发明授权

US07151303B2 Fully-depleted (FD) (SOI) MOSFET access transistor 有权
标题翻译：全耗尽（FD）（SOI）MOSFET存取晶体管
公开(公告)号：US07151303B2
公开(公告)日：2006-12-19
申请号：US10751443
申请日：2004-01-06
申请人： Hongmei Wang , John K. Zahurak
发明人： Hongmei Wang , John K. Zahurak
IPC分类号： H01L27/105 , H01L27/12
CPC分类号： H01L29/4908 , H01L21/84 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1203 , H01L29/78621
摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.
摘要翻译：公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

39. 发明申请

US20060046381A1 Methods of forming capacitor structures, methods of forming threshold voltage implant regions, and methods of implanting dopant into channel regions 失效
标题翻译：形成电容器结构的方法，形成阈值电压注入区域的方法以及将掺杂剂注入沟道区域的方法
公开(公告)号：US20060046381A1
公开(公告)日：2006-03-02
申请号：US10925736
申请日：2004-08-24
申请人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
发明人： Hongmei Wang , Kurt Beigel , Fred Fishburn , Rongsheng Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/324 , H01L21/823412 , H01L27/0811 , H01L27/088 , H01L29/66537 , H01L29/7833
摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.
摘要翻译：本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为在介电材料的下方并与导电掺杂的扩散区相邻。形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

40. 发明授权

US06977419B2 MOSFETs including a dielectric plug to suppress short-channel effects 有权
标题翻译： MOSFET包括电介质塞以抑制短沟道效应
公开(公告)号：US06977419B2
公开(公告)日：2005-12-20
申请号：US10931507
申请日：2004-09-01
申请人： Hongmei Wang , Zhongze Wang
发明人： Hongmei Wang , Zhongze Wang
IPC分类号： H01L21/336 , H01L29/06
CPC分类号： H01L29/66628 , H01L29/0649 , H01L29/0653 , H01L29/66636
摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.
摘要翻译：本发明提供了一种制造MOSFET中的电介质塞的技术。通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及在源极之间的沟道区域和漏区。

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