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31. 发明申请

US20110164693A1 INTERFACE CIRCUIT 审中-公开
标题翻译：接口电路
公开(公告)号：US20110164693A1
公开(公告)日：2011-07-07
申请号：US13047337
申请日：2011-03-14
申请人： Yoshihide KOMATSU , Tsuyoshi Ebuchi , Yukio Arima , Toru Iwata
发明人： Yoshihide KOMATSU , Tsuyoshi Ebuchi , Yukio Arima , Toru Iwata
IPC分类号： H04L27/00
CPC分类号： H04L7/0008 , G06F1/12 , H04L5/1469 , H04L5/16 , H04L25/0272 , H04L25/0298
摘要： An interface circuit including an LSI (10) in a host device (1), and an LSI (20) in a sub device (2), respectively. The LSI (10) generates a first transmission clock signal (TC1) and a first reception clock signal (RC1) separately in accordance with a first reference clock signal (RFC1). The LSI (10) also generates a second reference clock signal (RFC2) for a sub device (2). The reference clock signal (RFC2) is converted into a differential clock signal, and then transmitted to the sub device (2). An LSI (20) of the sub device (2) generates a second transmission clock signal (TC2) and a second reception clock signal (RC2) separately in accordance with a third reference clock signal (RFC3) converted from the differential clock signal.
摘要翻译：一种在主机（1）中包括LSI（10）的接口电路和分装置（2）中的LSI（20）。 LSI（10）根据第一参考时钟信号（RFC1）分别产生第一传输时钟信号（TC1）和第一接收时钟信号（RC1）。 LSI（10）还为子设备（2）生成第二参考时钟信号（RFC2）。参考时钟信号（RFC2）被转换为差分时钟信号，然后发送到子设备（2）。子装置（2）的LSI（20）根据从差分时钟信号转换的第三参考时钟信号（RFC3）分别产生第二传输时钟信号（TC2）和第二接收时钟信号（RC2）。

32. 发明授权

US07957498B2 Data receiver device and data transmission/reception system 有权
标题翻译：数据接收设备和数据发送/接收系统
公开(公告)号：US07957498B2
公开(公告)日：2011-06-07
申请号：US11995423
申请日：2006-07-10
申请人： Hirokazu Sugimoto , Toru Iwata
发明人： Hirokazu Sugimoto , Toru Iwata
IPC分类号： H04L7/00
CPC分类号： H04L7/0004 , H04L25/14
摘要： The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.
摘要翻译：数据接收装置包括：位相位同步电路（10），用于执行接收数据信号的相位调整，以设置数据信号与对应的时钟信号之间的预定相位关系; 一旦检测到输入到位相位同步电路（10）的数据信号基于由位相位同步电路（10）相位调整的数据信号而处于稳定状态，则输出检测信号的状态检测电路（20））和相应的时钟信号。位相位同步电路（10）在接收到检测信号时初始化数据信号的相位调整。

33. 发明授权

US07864252B2 Video signal processor capable of suppressing excessive heat generation, method using the same, display device and method using the same 有权
标题翻译：能够抑制过度发热的视频信号处理器，使用其的方法，显示装置及使用其的方法
公开(公告)号：US07864252B2
公开(公告)日：2011-01-04
申请号：US11071190
申请日：2005-03-04
申请人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
发明人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
IPC分类号： H04N5/63 , H04N17/00 , H04N5/44 , H03L7/00
CPC分类号： G09G5/006 , G09G3/2092
摘要： A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.
摘要翻译：用于根据输入时钟信号处理输入视频数据的视频信号处理器包括：输入部分，用于改变视频数据的格式并输出结果数据; 逻辑部分，用于对从输入部分输出的数据进行解码并输出解码数据; 以及频率检测器，用于检测时钟信号具有高于给定频率的频率，并将检测结果作为检测信号输出。当时钟信号的频率高于给定频率时，根据检测信号停止构成视频信号处理器的电路的至少一部分的操作。

34. 发明申请

US20090086852A1 DATA RECEIVER DEVICE AND DATA TRANSMISSION/RECEPTION SYSTEM 有权
标题翻译：数据接收设备和数据传输/接收系统
公开(公告)号：US20090086852A1
公开(公告)日：2009-04-02
申请号：US11995423
申请日：2006-07-10
申请人： Hirokazu Sugimoto , Toru Iwata
发明人： Hirokazu Sugimoto , Toru Iwata
IPC分类号： H04L7/06
CPC分类号： H04L7/0004 , H04L25/14
摘要： The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.
摘要翻译：数据接收装置包括：位相位同步电路（10），用于执行接收数据信号的相位调整，以设置数据信号与对应的时钟信号之间的预定相位关系; 一旦检测到输入到位相位同步电路（10）的数据信号基于由位相位同步电路（10）相位调整的数据信号而处于稳定状态，则输出检测信号的状态检测电路（20））和相应的时钟信号。位相位同步电路（10）在接收到检测信号时初始化数据信号的相位调整。

35. 发明申请

US20070183175A1 Charge pumping circuit 有权
标题翻译：充电泵电路
公开(公告)号：US20070183175A1
公开(公告)日：2007-08-09
申请号：US11637687
申请日：2006-12-13
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
IPC分类号： H02M7/00
CPC分类号： H02M3/07 , H03L7/0895 , H03L7/0896
摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.
摘要翻译：电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。推挽操作中的另一个用电流镜电路的输出电流进行。

36. 发明授权

US07030688B2 Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：用于PLL，锁相环和半导体集成电路的低通滤波器
公开(公告)号：US07030688B2
公开(公告)日：2006-04-18
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03K5/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

37. 发明授权

US06943595B2 Synchronization circuit 有权
标题翻译：同步电路
公开(公告)号：US06943595B2
公开(公告)日：2005-09-13
申请号：US10670510
申请日：2003-09-26
申请人： Hirokazu Sugimoto , Toru Iwata , Takashi Hirata
发明人： Hirokazu Sugimoto , Toru Iwata , Takashi Hirata
IPC分类号： H04L25/40 , H03K5/00 , H03K5/135 , H04L7/00 , H04L7/02 , H04L7/04 , H03L7/00
CPC分类号： H03K5/135 , H03K2005/00156 , H04L7/0008 , H04L7/02
摘要： A synchronization circuit includes a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock, a delay selection circuit for adding a delay to the input signal based on the control signal, and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.
摘要翻译：同步电路包括：状态检测电路，用于根据输入信号的转变点和同步时钟的边沿之间的时间关系输出控制信号;延迟选择电路，用于根据控制信号向输入信号添加延迟信号和用于使从延迟选择电路输出的信号与同步时钟同步的锁存电路。因此，可以在不增加输入信号的延迟的情况下执行输入信号的同步。

38. 发明授权

US06426985B1 Variable delay circuit and phase adjustment circuit 失效
标题翻译：可变延迟电路和相位调整电路
公开(公告)号：US06426985B1
公开(公告)日：2002-07-30
申请号：US09283888
申请日：1999-04-01
申请人： Toru Iwata , Hiroyuki Yamauchi
发明人： Toru Iwata , Hiroyuki Yamauchi
IPC分类号： H04L700
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0818
摘要： A variable delay circuit includes a plurality of delay circuits for delaying an input signal; and a selection circuit for selecting an output from one of the plurality of delay circuits in accordance with a selection signal. The plurality of delay circuits include a first delay circuit for delaying the input signal by a first delay time period and a second delay circuit for delaying the input signal by a second delay time period which is longer than the first delay time period. The difference between the first delay time period and the second delay time period is shorter than a minimum delay time period which is allowed to be set in the first delay circuit.
摘要翻译：可变延迟电路包括用于延迟输入信号的多个延迟电路; 以及选择电路，用于根据选择信号选择多个延迟电路之一的输出。多个延迟电路包括用于将输入信号延迟第一延迟时间段的第一延迟电路和用于将输入信号延迟比第一延迟时间段长的第二延迟时间段的第二延迟电路。第一延迟时间段和第二延迟时间段之间的差值比允许在第一延迟电路中设置的最小延迟时间段短。

39. 发明授权

US06208567B1 Semiconductor device capable of cutting off a leakage current in a defective array section 失效
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置
公开(公告)号：US06208567B1
公开(公告)日：2001-03-27
申请号：US09014775
申请日：1998-01-28
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C2900
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

40. 发明授权

US06199005B1 Vehicle drive force control device 失效
标题翻译：车辆驱动力控制装置
公开(公告)号：US06199005B1
公开(公告)日：2001-03-06
申请号：US09066816
申请日：1998-04-28
申请人： Toru Iwata
发明人： Toru Iwata
IPC分类号： G06F700
CPC分类号： B60W10/06 , B60K28/165 , B60W10/04 , B60W10/101 , B60W30/18 , B60W30/1819 , B60W2510/0638 , B60W2510/0657 , B60W2710/0616 , F16H61/0213 , F16H61/66 , Y10T477/623 , Y10T477/6242 , Y10T477/62427
摘要： A slip of drive wheels of a vehicle driven via a continuously variable transmission is suppressed due to fuel cut of a multi-cylinder engine. The speed change response characteristics of the transmission are made to vary according to the engine rotation speed when fuel cut is performed. A speed change ratio command value is calculated from a target speed change ratio based on a first-order delay due to a predetermined time-constant. The response of the transmission is thus delayed for low engine rotation speed than for high rotation speed, and undesirable fluctuation of the speed change ratio when the drive wheels slip is prevented.
摘要翻译：通过多缸发动机的燃料切断，能够抑制由无级变速器驱动的车辆的驱动轮滑动。当进行燃料切断时，变速器的变速响应特性根据发动机转速而变化。基于由于预定时间常数导致的一阶延迟，从目标速度变化率计算出变速比指令值。因此，与低转速相比，变速箱的响应低于发动机转速，并且防止驱动轮滑动时的变速比的不期望的波动。

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