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31. 发明申请

US20140070357A1 SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS 有权
标题翻译：具有嵌入式衬垫的SOI器件限制STI感染
公开(公告)号：US20140070357A1
公开(公告)日：2014-03-13
申请号：US13611182
申请日：2012-09-12
申请人： Kangguo Cheng , Balasubramanian S. Haran , Shom Ponoth
发明人： Kangguo Cheng , Balasubramanian S. Haran , Shom Ponoth
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L27/1203 , H01L21/31144 , H01L21/76283 , H01L21/84 , H01L29/06 , H01L29/66772 , H01L29/78654
摘要： A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.
摘要翻译：具有隔离区域的半导体基板及其形成方法。该方法包括以下步骤：提供具有衬底层，掩埋氧化物（BOX），绝缘体上硅（SOI）层，衬垫氧化物层和衬垫氮化物层的衬底，形成浅沟槽区，蚀刻衬垫氧化层以形成耳朵并蚀刻BOX层以形成底切，在浅沟槽区域上沉积衬垫，在浅沟槽区域的表面上沉积软掩模，填充浅沟槽区域，蚀刻软掩模，使得它凹陷到BOX层的顶部，在某些区域蚀刻衬垫，去除软掩模，以及填充和抛光浅沟槽区域。当触点不对准时，衬垫防止半导体器件的短路。

32. 发明申请

US20140048804A1 FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL 审中-公开
公开(公告)号：US20140048804A1
公开(公告)日：2014-02-20
申请号：US13589427
申请日：2012-08-20
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Chun-Chen Yeh
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Chun-Chen Yeh
IPC分类号： H01L29/04
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L29/66795
摘要： A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.

33. 发明授权

US08652898B2 Integrated circuit with a thin body field effect transistor and capacitor 失效
标题翻译：具有薄体场效应晶体管和电容器的集成电路
公开(公告)号：US08652898B2
公开(公告)日：2014-02-18
申请号：US13614908
申请日：2012-09-13
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/77
CPC分类号： H01L21/84 , H01L21/32053 , H01L21/823814 , H01L27/0629 , H01L27/1203 , H01L29/41783
摘要： A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.
摘要翻译：隔离第一半导体层中的第一半导体层和电容器区域的晶体管区域。在晶体管区域的第一半导体层上形成虚拟栅极结构。在第一半导体层上形成第二半导体层。第二半导体层的第一和第二部分位于晶体管区域中，第二半导体层的第三部分位于电容器区域中。第一，第二和第三硅化物区分别形成在第二半导体层的第一，第二和第三部分上。在形成电介质层之后，去除伪栅极结构形成第一腔。位于第三硅化物区域上方的电介质层的至少一部分被去除，形成第二腔。在第一腔中形成栅极电介质，在第二腔中形成电容器电介质。

34. 发明申请

US20140038369A1 METHOD OF FORMING FIN-FIELD EFFECT TRANSISTOR (finFET) STRUCTURE 有权
标题翻译：形成Fin场效应晶体管（finFET）结构的方法
公开(公告)号：US20140038369A1
公开(公告)日：2014-02-06
申请号：US13565838
申请日：2012-08-03
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/845 , H01L27/1211
摘要： Various embodiments include methods of forming semiconductor structures. In one embodiment, a method includes: providing a precursor structure including a substrate and a set of fins overlying the substrate; forming a dummy epitaxy between the fins in the set of fins; masking a first group of fins in the set of fins and the dummy epitaxy between the first group of fins in the set of fins; removing the dummy epitaxy to expose a second group of the fins; forming a first in-situ doped epitaxy between the exposed fins; masking the second group of fins in the set of fins and the in-situ doped epitaxy between the second group of fins in the set of fins; unmasking the first group of fins; removing the dummy epitaxy layer between the first group of fins to expose of the first group of fins; and forming a second in-situ doped epitaxy between the exposed fins.
摘要翻译：各种实施例包括形成半导体结构的方法。在一个实施例中，一种方法包括：提供包括衬底和覆盖衬底的一组鳍片的前体结构; 在翅片组中的翅片之间形成虚拟外延; 掩蔽该组散热片中的第一组散热片和在一组翅片中的第一组翅片之间的虚设外延; 去除所述虚拟外延以暴露第二组散热片; 在暴露的翅片之间形成第一原位掺杂外延; 掩蔽该组散热片中的第二组翅片和在该组翅片中的第二组翅片之间的原位掺杂的外延; 揭开第一组翅片; 去除第一组翅片之间的虚拟外延层以暴露第一组翅片; 以及在所述暴露的鳍之间形成第二原位掺杂的外延。

35. 发明授权

US08642415B2 Semiconductor substrate with transistors having different threshold voltages 失效
标题翻译：具有不同阈值电压的晶体管的半导体衬底
公开(公告)号：US08642415B2
公开(公告)日：2014-02-04
申请号：US13487511
申请日：2012-06-04
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.
摘要翻译：公开了一种制造半导体集成电路的方法。该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

36. 发明申请

US20140001561A1 CMOS DEVICES HAVING STRAIN SOURCE/DRAIN REGIONS AND LOW CONTACT RESISTANCE 审中-公开
标题翻译：具有应变源/漏区的CMOS器件和低接触电阻
公开(公告)号：US20140001561A1
公开(公告)日：2014-01-02
申请号：US13534522
申请日：2012-06-27
申请人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Thomas N. Adam
发明人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Thomas N. Adam
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： A CMOS device structure and method of manufacturing the same are provided. The CMOS device structure includes a substrate having a first region and a second region. The CMOS device structure further includes a first gate formed in the first region overlying a first channel region in the substrate. The CMOS device structure further includes a first pair of source/drain regions formed in the first region on either side of the first channel region. Each region of the pair of source/drain regions has a substantially V-shaped concave top surface.
摘要翻译：提供了一种CMOS器件结构及其制造方法。 CMOS器件结构包括具有第一区域和第二区域的衬底。 CMOS器件结构还包括形成在覆盖衬底中的第一沟道区域的第一区域中的第一栅极。 CMOS器件结构还包括形成在第一沟道区两侧的第一区域中的第一对源/漏区。一对源极/漏极区域中的每个区域具有大致V形的凹顶表面。

37. 发明授权

US08617937B2 Forming narrow fins for finFET devices using asymmetrically spaced mandrels 有权
标题翻译：使用不对称间隔的心轴形成finFET器件的窄鳍
公开(公告)号：US08617937B2
公开(公告)日：2013-12-31
申请号：US12886850
申请日：2010-09-21
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
IPC分类号： H01L21/335
CPC分类号： H01L29/66795 , H01L21/845
摘要： A method of forming fins for fin-shaped field effect transistor (finFET) devices includes forming a plurality of sacrificial mandrels over a semiconductor substrate. The plurality of sacrificial mandrels are spaced apart from one another by a first distance along a first direction, and by a second distance along a second direction. Spacer layers are formed on sidewalls of the sacrificial mandrels such that portions of the spacer layers between sacrificial mandrels along the first direction are merged together. Portions of the spacer layers between sacrificial mandrels along the second direction remain spaced apart. The sacrificial mandrels are removed. A pattern corresponding to the spacer layers is transferred into the semiconductor layers to form a plurality of semiconductor fins. Adjacent pairs of fins are merged with one another at locations corresponding to the merged spacer layers.
摘要翻译：形成鳍状场效应晶体管（finFET）器件的鳍片的方法包括在半导体衬底上形成多个牺牲心轴。多个牺牲心轴沿着第一方向彼此间隔开第一距离，并且沿第二方向间隔开第二距离。间隔层形成在牺牲心轴的侧壁上，使得沿着第一方向的牺牲心轴之间的间隔层的部分被合并在一起。沿着第二方向的牺牲心轴之间的间隔层的部分保持间隔开。牺牲心轴被去除。对应于间隔层的图案被转移到半导体层中以形成多个半导体鳍片。相邻的翅片对在与合并的间隔层相对应的位置处彼此合并。

38. 发明申请

US20130334580A1 REPLACEMENT METAL GATE PROCESSING WITH REDUCED INTERLEVEL DIELECTRIC LAYER ETCH RATE 审中-公开
标题翻译：替代金属栅加工具有降低的交替介电层蚀刻速率
公开(公告)号：US20130334580A1
公开(公告)日：2013-12-19
申请号：US13527828
申请日：2012-06-20
申请人： Kangguo Cheng , Junli Wang , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Kangguo Cheng , Junli Wang , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure includes an interlevel dielectric (ILD) layer disposed over a semiconductor substrate and a transistor gate structure formed on the substrate; and a shallow gas cluster ion beam (GCIB) layer infused in a top portion of the ILD layer; wherein the GCIB layer has a slower etch rate with respect to the ILD layer.
摘要翻译：半导体结构包括设置在半导体衬底上的层间电介质（ILD）层和形成在衬底上的晶体管栅极结构; 和注入ILD层顶部的浅层气体簇离子束（GCIB）层; 其中GCIB层相对于ILD层具有较慢的蚀刻速率。

39. 发明授权

US08598664B2 Field effect transistor (FET) and method of forming the FET without damaging the wafer surface 有权
标题翻译：场效应晶体管（FET）和形成FET而不损坏晶片表面的方法
公开(公告)号：US08598664B2
公开(公告)日：2013-12-03
申请号：US13420763
申请日：2012-03-15
申请人： Kangguo Cheng , Bruce B. Doris , Yu Zhu
发明人： Kangguo Cheng , Bruce B. Doris , Yu Zhu
IPC分类号： H01L27/12
CPC分类号： H01L21/28 , H01L29/78
摘要： Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.
摘要翻译：公开了场效应晶体管结构和形成该结构的方法。栅极叠层形成在指定沟道区上方的晶片上。间隔物材料被沉积并各向异性蚀刻，直到暴露晶片或栅极堆叠的任何水平表面之前，从而在晶片表面上留下相对薄的间隔物材料的水平部分和栅极侧壁上的间隔物材料的相对较厚的垂直部分。剩余的间隔物料被选择性地和各向同性地蚀刻，直到间隔物材料的水平部分被完全去除，从而仅留下间隔材料在浇口侧壁上的垂直部分。该选择性各向同性蚀刻除去间隔材料的水平部分而不损坏晶片表面。可以在与栅极侧壁间隔物相邻的未损坏的晶片表面上形成凸出的外延源极/漏极区域，以便定制源极/漏极电阻值。

40. 发明申请

US20130313651A1 INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES 有权
公开(公告)号：US20130313651A1
公开(公告)日：2013-11-28
申请号：US13478080
申请日：2012-05-22
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/07 , H01L21/8238
CPC分类号： H01L27/0629 , H01L29/0847 , H01L29/8611 , H01L29/868
摘要： An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.

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