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    • 37. 发明授权
    • Method and apparatus for at-speed testing of digital circuits
    • 用于数字电路高速测试的方法和装置
    • US07437636B2
    • 2008-10-14
    • US11265488
    • 2005-11-01
    • Janusz RajskiAbu HassanRobert ThompsonNagesh Tamarapalli
    • Janusz RajskiAbu HassanRobert ThompsonNagesh Tamarapalli
    • G01R31/28G06F11/00G06F1/04
    • G01R31/318594G01R31/31858
    • Exemplary schemes for multi-frequency at-speed logic Built-In Self Test (BIST) are provided. For example, certain schemes allow at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. Some of the disclosed schemes are also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. In particular embodiments, the loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. In certain embodiments, only the capture cycle is performed at the corresponding system timing. In some embodiments, a programmable capture window makes it possible to test every intra- and inter-domain at-speed without the negative impact of clock skew between clock domains.
    • 提供了多频率高速逻辑内置自检(BIST)的示范方案。 例如,某些方案允许对由外部或片上产生的时钟信号控制的非常高频率的集成电路进行高速测试。 所公开的方案中的一些也适用于具有可以是相同频率或不同频率的多个时钟域的电路的测试。 在特定实施例中,扫描链的加载和卸载与各个域之间的逻辑的速度测试分离,并且可以以比速度测试更快或更慢的频率进行。 在某些实施例中,在对应的系统定时仅执行捕获周期。 在一些实施例中,可编程捕获窗口使得可以在时钟域之间没有时钟偏移的负面影响的情况下测试每个域内和域间的速度。