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31. 发明授权

US5926700A Semiconductor fabrication having multi-level transistors and high density interconnect therebetween 失效
标题翻译：具有多电平晶体管和其间的高密度互连的半导体制造
公开(公告)号：US5926700A
公开(公告)日：1999-07-20
申请号：US850871
申请日：1997-05-02
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L21/822 , H01L27/06 , H01L21/336
CPC分类号： H01L27/0688 , H01L21/8221
摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure. Select portions of the primary and secondary interlevel dielectrics are then removed to expose one of the junctions and a portion of the doped polysilicon structure arranged proximate this junction. An interconnect is formed contiguously between the junction and the polysilicon structure by depositing a conductive material within the removed portions.
摘要翻译：提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构。升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。提供晶体管，其包括在一对结之间间隔开的栅极导体。在晶体管两端沉积初级层间电介质。在初级层间电介质的上表面的选择部分内形成多晶硅结构。多晶硅结构是距离晶体管的上方和横向距离之间的间隔距离。将掺杂剂注入到多晶硅结构中。次级层间电介质沉积在初级层间电介质和掺杂多晶硅结构之间。选择部分初级和次级层间电介质然后被去除以暴露出一个结点，并且掺杂多晶硅结构的一部分布置在该结附近。通过在去除的部分内沉积导电材料，在结和多晶硅结构之间连续地形成互连。

32. 发明授权

US5904529A Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate 失效
公开(公告)号：US5904529A
公开(公告)日：1999-05-18
申请号：US918202
申请日：1997-08-25
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/28123 , H01L21/823418 , H01L29/7835
摘要： A method of making an asymmetrical IGFET and isolating active regions is disclosed. The method includes providing a semiconductor substrate with an active region and a field region, wherein the active region includes a source region and a drain region, and the active region is adjacent to the field region, forming a dielectric layer over the substrate, forming a first etch mask over the dielectric layer, etching a selected portion of the dielectric layer beneath an opening in the first etch mask, wherein a first unetched portion of the dielectric layer provides a field dielectric over the field region, a second unetched portion of the dielectric layer provides a drain-protect dielectric over the drain region, and the dielectric layer is removed above the source region, forming a gate insulator on a portion of the active region outside the drain-protect dielectric, depositing a gate material over the drain-protect dielectric and the gate insulator, polishing the gate material so that a portion of the gate material over the drain-protect dielectric is removed, forming a second etch mask over the gate material, etching the gate material beneath an opening in the second etch mask to remove a portion of the gate material over the source region, wherein an unetched portion of the gate material forms a gate, and a sidewall of the gate is adjacent to a sidewall of the drain-protect dielectric, implanting a dopant into the active region during a first implant step, wherein a greater concentration of the dopant is implanted in the source region than in the drain region due to the drain-protect dielectric, and forming a source in the source region and a drain in the drain region. Advantageously, the dielectric layer provides both the field dielectric and the drain-protect dielectric to reduce process steps, and the IGFET has low source-drain resistance and reduces hot carrier effects.

33. 发明授权

US5888872A Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall 失效
标题翻译：用于形成在侧壁间隔件和蚀刻的侧向侧壁之间自对准的源漏接合区域的方法
公开(公告)号：US5888872A
公开(公告)日：1999-03-30
申请号：US879574
申请日：1997-06-20
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L21/60 , H01L21/768 , H01L21/822 , H01L23/522 , H01L27/06 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/76838 , H01L21/8221 , H01L23/5226 , H01L27/0688 , H01L2924/0002
摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer. The second transistor has a pair of implant regions spaced from each other by a gate conductor and a pair of oxide spacers arranged on opposed sidewall surfaces of the gate conductor. Part of the polysilicon layer is removed such that polysilicon only extends under the gate conductor and terminates a pre-defined distance from each of the pair of oxide spacers. A pair of junctions remain for the second transistor that are defined between an etched lateral edge and an oxide spacer. A second interlevel dielectric may be deposited across the second transistor and exposed areas of the primary interlevel dielectric to isolate the transistor from other active devices.
摘要翻译：提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构并将其与位于同一高架平面中的另一多晶硅结构隔离。升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。提供了第一晶体管，其设置在硅基衬底上并且位于硅基衬底内。在晶体管和衬底两端沉积初级层间电介质。然后可以将多晶硅沉积在初级层间电介质上并使用离子注入进行掺杂。可以在多晶硅层的一部分上形成第二晶体管。第二晶体管具有通过栅极导体和布置在栅极导体的相对的侧壁表面上的一对氧化物隔离物彼此隔开的一对注入区域。去除多晶硅层的一部分，使得多晶硅仅在栅极导体下方延伸并且终止与一对氧化物间隔物中的每一个的预定距离。在蚀刻的侧边缘和氧化物间隔物之间限定的第二晶体管保留一对结。可以跨越第二晶体管和初级层间电介质的暴露区域沉积第二层间电介质以将晶体管与其它有源器件隔离。

34. 发明授权

US5872038A Semiconductor device having an elevated active region formed in an oxide trench and method of manufacture thereof 失效
标题翻译：具有在氧化物沟槽中形成的有源区域升高的半导体器件及其制造方法
公开(公告)号：US5872038A
公开(公告)日：1999-02-16
申请号：US780643
申请日：1997-01-08
申请人： Michael Duane , Daniel Kadosh , Mark I. Gardner
发明人： Michael Duane , Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/225 , H01L21/336 , H01L21/768 , H01L29/417 , H01L29/78
CPC分类号： H01L29/66568 , H01L21/76877 , H01L29/41725 , H01L29/41733 , H01L29/66575 , H01L29/7833 , H01L21/2257 , H01L29/665 , Y10S257/90
摘要： A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.
摘要翻译：公开了一种用于形成具有升高的有源区的半导体器件的工艺。该工艺包括在半导体衬底上形成多个栅电极，并在栅电极上设置厚氧化层。在厚的氧化物层中形成沟槽并填充有多晶硅材料。随后掺杂多晶硅材料以便在衬底的有源区上方形成升高的有源区。

35. 发明授权

US5869379A Method of forming air gap spacer for high performance MOSFETS' 失效
标题翻译：形成用于高性能MOSFET的气隙间隔物的方法
公开(公告)号：US5869379A
公开(公告)日：1999-02-09
申请号：US987116
申请日：1997-12-08
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/665 , H01L29/4991 , H01L29/66598 , H01L29/7833
摘要： A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the gate conductor. A source/drain implant self-aligned to opposed lateral sidewalls of the masking structure is performed to form source/drain implant areas within the substrate. Select portions of the gate conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the gate conductor. A lightly doped drain implant self-aligned to the opposed sidewall surfaces of the narrowed gate conductor is performed to form lightly doped drain implant areas within the substrate. An interlevel dielectric is deposited to a level above the gate conductor across the semiconductor topography such that air gaps are formed laterally adjacent the opposed sidewall surfaces of the gate conductor, and the interlevel dielectric is planarized to a level substantially coplanar with an upper surface of the masking structure. In an alternative embodiment, a refractory metal is deposited across an upper surface of the masking structure and across the source/drain implant areas subsequent to forming said source/drain implant areas. The refractory metal is heated to form a metal silicide overlying the source/drain implant areas and residual refractory metal is removed from above the masking structure. In yet another alternative embodiment, a single high-energy ion implant is used to simultaneously form the source/drain implant area and the lightly doped drain implant area following removal of select portions of the gate conductors.
摘要翻译：提供一种形成晶体管的方法，其中集成电路采用的栅极导体和相邻结构之间的电容耦合减小。根据实施例，栅极导体在半导体衬底之上介电间隔开，并且掩模结构布置在栅极导体的上表面上。执行与掩模结构的相对的侧向侧壁自对准的源极/漏极注入以在衬底内形成源极/漏极注入区域。选择栅极导体的部分被去除，使得掩模结构的相对端延伸超过栅极导体的相对的侧壁表面。执行与窄化栅极导体的相对侧壁表面自对准的轻掺杂漏极注入，以在衬底内形成轻掺杂的漏极注入区域。跨越半导体拓扑结构的层间电介质沉积到栅极导体上方的一个电平，使得气隙横向邻近栅极导体的相对的侧壁表面形成，并且层间电介质平坦化到基本上与平面的共面平面掩蔽结构。在替代实施例中，在形成所述源极/漏极注入区域之后，跨越掩模结构的上表面并横跨源极/漏极注入区域沉积难熔金属。难熔金属被加热以形成覆盖在源极/漏极注入区域上的金属硅化物，并且从掩蔽结构上方除去残留的难熔金属。在另一替代实施例中，在去除栅极导体的选择部分之后，单个高能离子注入用于同时形成源极/漏极注入区域和轻掺杂漏极注入区域。

36. 发明授权

US5834354A Ultra high density NOR gate using a stacked transistor arrangement 失效
标题翻译：使用堆叠晶体管布置的超高密度NOR门
公开(公告)号：US5834354A
公开(公告)日：1998-11-10
申请号：US745031
申请日：1996-11-07
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/336 , H01L29/76 , H01L31/036
CPC分类号： H01L21/8221 , H01L27/0688
摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allow development of a high density NOR gate. The NOR gate includes two pairs of stacked transistors, wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair.
摘要翻译：提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。多级制造过程不仅增加了整体电路密度，而且重点放在了在不同级别上的器件之间的高性能互连。互连配置在一个晶体管电平内的特征之间尽可能短，在另一个晶体管级内的特征。该互连方案通过在较低级晶体管的栅极导体上形成上级晶体管的栅极导体来降低电阻率。或者，栅极导体可以是单个导电实体。为了将栅导体邻接在一起或形成单个栅极导体，上层晶体管相对于下层晶体管反相。除了反向共享栅极导体之外，多级晶体管制造工艺包括形成开口和填充这些开口以产生与上/下晶体管的结的互连。将一对堆叠晶体管的栅极导体和这些晶体管的连接特定结之间的互连允许开发高密度的或非门。 NOR门包括两对堆叠晶体管，其中一对晶体管可以连接到该对的另一个晶体管或连接到另一对的一个或两个晶体管。

37. 发明授权

US5795807A Semiconductor device having a group of high performance transistors and method of manufacture thereof 失效
公开(公告)号：US5795807A
公开(公告)日：1998-08-18
申请号：US771131
申请日：1996-12-20
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/265
CPC分类号： H01L21/823425 , H01L27/088
摘要： A semiconductor device may be fabricated using a process in which a group of transistors connected between a high and low voltage sources are formed. The transistor among the group of transistors which is used for connection to the high voltage source has non-symmetrical source and drain regions. The device, exploits low operating voltages to construct new high performance transistors.

38. 发明授权

US5789787A Asymmetrical N-channel and P-channel devices 失效
公开(公告)号：US5789787A
公开(公告)日：1998-08-04
申请号：US963897
申请日：1997-11-04
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/76
CPC分类号： H01L21/823814 , H01L27/0922
摘要： An asymmetrical N-channel IGFET and an asymmetrical P-channel IGFET are disclosed. One or both IGFETs include a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region. Preferably, the heavily doped source region and lightly doped drain region provide channel junctions. Forming a first asymmetrical IGFET includes forming a gate with first and second opposing sidewalls over a first active region, applying a first ion implantation to implant lightly doped source and drain regions into the first active region, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped source region outside the first spacer into an ultra-heavily doped source region without doping a portion of the heavily doped source region beneath the first spacer, and to convert a portion of the lightly doped drain region outside the second spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the second spacer. A second asymmetrical IGFET is formed in a related manner. Advantageously, one or both IGFETs have low source-drain series resistance and reduce hot carrier effects.

39. 发明授权

US5770483A Multi-level transistor fabrication method with high performance drain-to-gate connection 失效
标题翻译：具有高性能漏极 - 栅极连接的多电平晶体管制造方法
公开(公告)号：US5770483A
公开(公告)日：1998-06-23
申请号：US729795
申请日：1996-10-08
申请人： Daniel Kadosh , Mark I. Gardner , Fred N. Hause
发明人： Daniel Kadosh , Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/768 , H01L21/822 , H01L23/48 , H01L27/06 , H01L21/00 , H01L21/84
CPC分类号： H01L27/0688 , H01L21/8221 , H01L23/485 , H01L23/535 , H01L2924/0002
摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between the drain region of an upper level transistor to the gate of a lower level transistor so as to effect a direct coupling between the output of one transistor to the input of another. Direct coupling in this fashion affords a lower propagation delay and therefore achieves the benefit of a higher performance, faster switching circuit.
摘要翻译：提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。多级制造工艺不仅增加了整体电路密度，而且重点放在了在不同层次的器件之间的互连上。因此，引入了高性能互连，由此在一个晶体管级内的特征之间使互连尽可能短以达到另一晶体管级内的特征。互连采用直接在上级晶体管的漏极区域到低级晶体管的栅极之间的通孔，以便实现一个晶体管的输出与另一晶体管的输入之间的直接耦合。以这种方式的直接耦合提供较低的传播延迟，从而实现更高性能，更快速的开关电路的益处。

40. 发明授权

US5770482A Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto 失效
公开(公告)号：US5770482A
公开(公告)日：1998-06-23
申请号：US727049
申请日：1996-10-08
申请人： Daniel Kadosh , Mark I. Garnder , Jon D. Cheek
发明人： Daniel Kadosh , Mark I. Garnder , Jon D. Cheek
IPC分类号： H01L21/768 , H01L21/822 , H01L23/48 , H01L27/06 , H01L21/00 , H01L21/84
CPC分类号： H01L21/8221 , H01L23/485 , H01L23/535 , H01L27/0688 , H01L2924/0002
摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a well of an upper level transistor to a well of a lower transistor so as to effect direct coupling between the wells of the respective transistors. Direct coupling in this fashion affords consistent operation of transistors arranged on separate elevation levels. The via is made as short as possible so as to reduce any discrepancy in substrate/well voltage potential. This ensures predictable operation of transistors fashioned on separate elevation levels.

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