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31. 发明授权

US07042795B2 Flash memory device with burst read mode of operation 失效
公开(公告)号：US07042795B2
公开(公告)日：2006-05-09
申请号：US10816979
申请日：2004-04-02
申请人： Seung-Keun Lee , Jin-Sung Park
发明人： Seung-Keun Lee , Jin-Sung Park
IPC分类号： G11C8/00
CPC分类号： G11C7/1027 , G11C7/12 , G11C7/18 , G11C16/24 , G11C16/26 , G11C2207/005
摘要： A flash memory device is disclosed that includes a number of columns each of which is connected with a plurality of memory cells. A column selector circuit selects a part of the columns in response to a column address, and a plurality of sense amplifier groups are connected with the selected columns by the column selector circuit. The column selector circuit variably selects the columns according to whether the column address is 4N-aligned (where N is an integer having a value of 1 or more). For example, the column selector circuit chooses columns of the column address when the column address is 4N-aligned, and chooses columns of an upper column address when the column address is not 4N-aligned.

32. 发明授权

US07016232B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07016232B2
公开(公告)日：2006-03-21
申请号：US10922122
申请日：2004-08-18
申请人： Seung-Won Lee , Seung-Keun Lee
发明人： Seung-Won Lee , Seung-Keun Lee
IPC分类号： G12C16/00
CPC分类号： G11C7/062 , G11C7/18 , G11C16/04 , G11C16/28 , G11C29/24 , G11C29/50004
摘要： A memory device in accordance with embodiments of the present invention includes a reference cell array and a plurality of banks. Each of the banks includes memory cells. A plurality of current copier circuits corresponds to the banks, respectively. Each of the current copier circuits copies a reference current flowing through a reference cell array to generate a reference voltage. A plurality of sense blocks correspond to the banks, respectively. Each of the sense blocks includes a plurality of sense amplifiers for sensing data from a corresponding bank in response to the reference voltage from the corresponding current copier circuit. Memory cell lay-out area is reduced, and sense speed is increased.
摘要翻译：根据本发明的实施例的存储器件包括参考单元阵列和多个存储体。每个银行都包含存储单元。多个当前复印机电路分别对应于存储体。每个当前复印机电路复制流过参考单元阵列的参考电流以产生参考电压。多个感测块分别对应于存储体。每个感测块包括多个读出放大器，用于响应于来自相应的当前复印机电路的参考电压来感测来自相应存储体的数据。存储单元布局区域减少，感测速度提高。

33. 发明申请

US20050190603A1 Multi level flash memory device and program method 失效
标题翻译：多级闪存设备和程序方法
公开(公告)号：US20050190603A1
公开(公告)日：2005-09-01
申请号：US11021181
申请日：2004-12-22
申请人： Seung-Keun Lee , Dong-Ho Park
发明人： Seung-Keun Lee , Dong-Ho Park
IPC分类号： G11C16/00 , G11C11/34 , G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： We describe a multi level flash memory device and program method. The multi level flash memory device includes a plurality of memory cells, each storing an amount of charge indicative of more than two possible states and control circuitry coupled to the memory cells. The control circuitry to applying a programming voltage alternating with a verification voltage to the memory cells until all are at a desired state and applying at least one additional programming voltage to the cells in a highest state without applying a verification voltage. The method includes applying at least one programming pulse to the cells, verifying that each cell has reached the desired state, selecting the cells that are programmed for a highest state, and applying at least one additional programming pulse to the selected cells without further verifying their state.
摘要翻译：我们描述一个多级闪存设备和程序方法。多级闪存器件包括多个存储器单元，每个存储器单元存储指示多于两种可能状态的电荷量以及耦合到存储器单元的控制电路。控制电路，用于将编程电压与验证电压交替地施加到存储器单元，直到全部处于期望状态，并且在不施加验证电压的情况下以最高状态向单元施加至少一个附加编程电压。该方法包括向单元施加至少一个编程脉冲，验证每个单元已经达到期望状态，选择被编程为最高状态的单元，以及向选定单元施加至少一个附加编程脉冲，而不进一步验证它们州。

34. 发明授权

US06507522B2 Method for erasing memory cells in a nonvolatile memory 有权
标题翻译：擦除非易失性存储器中存储单元的方法
公开(公告)号：US06507522B2
公开(公告)日：2003-01-14
申请号：US09841917
申请日：2001-04-24
申请人： Joon-Sung Lee , Chan-Jo Lee , Yun-Heub Song , Seung-Keun Lee
发明人： Joon-Sung Lee , Chan-Jo Lee , Yun-Heub Song , Seung-Keun Lee
IPC分类号： G11C1604
CPC分类号： G11C16/3477 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3468
摘要： A method for managing memory cells in a nonvolatile memory, such as a flash memory, includes detecting and intermediately programming fast-erased memory cells. All of the memory cells in a sector can then be erased.
摘要翻译：用于管理非易失性存储器（诸如闪速存储器）中的存储器单元的方法包括检测和中间编程快速擦除的存储器单元。然后可以擦除扇区中的所有存储单元。

35. 发明授权

US5390150A Semiconductor memory device with redundancy structure suppressing power consumption 失效
标题翻译：具有抑制功耗的冗余结构的半导体存储器件
公开(公告)号：US5390150A
公开(公告)日：1995-02-14
申请号：US934918
申请日：1992-08-25
申请人： Choong-Keun Kwak , Seung-Keun Lee
发明人： Choong-Keun Kwak , Seung-Keun Lee
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C13/00
CPC分类号： G11C29/785 , G11C29/83 , G11C29/832
摘要： A semiconductor memory device with a redundancy circuit comprising fuses for selectively blocking the supply of the power voltage to the bit line pair, in order to minimize the power consumption originated from the contacting of the bit line to ground caused by a processing failure on the bit lines in stand-by state even though a column replacement is performed.
摘要翻译：一种具有冗余电路的半导体存储器件，该冗余电路包括用于选择性地阻断对位线对的电源电压供应的保险丝，以便最小化由位上的位线与地之间的接触引起的功率消耗即使进行列替换，仍处于待机状态。

36. 发明授权

US07656714B2 Bitline bias circuit and nor flash memory device including the bitline bias circuit 有权
标题翻译：位线偏置电路和不包括位线偏置电路的闪存器件
公开(公告)号：US07656714B2
公开(公告)日：2010-02-02
申请号：US11265218
申请日：2005-11-02
申请人： Hong-Soo Jeon , Seung-Keun Lee
发明人： Hong-Soo Jeon , Seung-Keun Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/24 , G11C5/145
摘要： The NOR flash memory device according to the present invention is operated by a high voltage supplied from bitline selection transistors and includes a bitline bias circuit for supplying a bias voltage of a constant level to the bitline bias transistor. In accordance with the present invention, it is possible to stably supply a desired voltage closing to a power voltage to the bitline bias transistor.
摘要翻译：根据本发明的NOR闪速存储器件通过从位线选择晶体管提供的高电压来操作，并且包括用于向位线偏置晶体管提供恒定电平的偏置电压的位线偏置电路。根据本发明，可以稳定地向位线偏置晶体管提供关闭到电源电压的期望电压。

37. 发明授权

US07394719B2 Flash memory device with burst read mode of operation 失效
标题翻译：具有突发读取操作模式的闪存设备
公开(公告)号：US07394719B2
公开(公告)日：2008-07-01
申请号：US11345995
申请日：2006-02-01
申请人： Seung-Keun Lee , Jin-Sung Park
发明人： Seung-Keun Lee , Jin-Sung Park
IPC分类号： G11C8/00
CPC分类号： G11C7/1027 , G11C7/12 , G11C7/18 , G11C16/24 , G11C16/26 , G11C2207/005
摘要： A flash memory device that includes a number of columns each of which is connected with a plurality of memory cells. A column selector circuit selects a part of the columns in response to a column address, and a plurality of sense amplifier groups are connected with the selected columns by the column selector circuit. The column selector circuit variably selects the columns according to whether the column address is 4N-aligned (where N is an integer having a value of 1 or more). For example, the column selector circuit chooses columns of the column address when the column address is 4N-aligned, and chooses columns of an upper column address when the column address is not 4N-aligned.
摘要翻译：一种闪速存储器件，其包括多个列，每个列与多个存储器单元连接。列选择器电路响应于列地址选择列的一部分，并且多个读出放大器组通过列选择器电路与所选择的列连接。列选择器电路根据列地址是否4N对齐（其中N是具有1或更大的值的整数）可变地选择列。例如，当列地址为4N对齐时，列选择器电路选择列地址的列，并且当列地址不是4N对齐时选择列列地址的列。

38. 发明申请

US20060133147A1 Nonvolatile semiconductor memory device and voltage generating circuit for the same 失效
标题翻译：非易失性半导体存储器件和电压产生电路相同
公开(公告)号：US20060133147A1
公开(公告)日：2006-06-22
申请号：US11262759
申请日：2005-11-01
申请人： Doo-Sub Lee , Seung-Keun Lee
发明人： Doo-Sub Lee , Seung-Keun Lee
IPC分类号： G11C16/04 , G11C5/14
CPC分类号： G11C16/30
摘要： A nonvolatile semiconductor memory device includes a memory cell array of a plurality of memory cells; and a voltage generating circuit for generating a programming voltage to be applied to the memory cells. The voltage generating circuit includes a first voltage generating unit for generating a negative voltage through a first charge pump; and a second voltage generating unit for generating a positive voltage through a second charge pump. During an accelerated programming operation, the first voltage generating unit increases a pumping efficiency of the first charge pump using an external power supply voltage, and the second voltage generating unit directly outputs the external power supply voltage.
摘要翻译：非易失性半导体存储器件包括多个存储器单元的存储单元阵列; 以及用于产生要施加到存储单元的编程电压的电压产生电路。电压产生电路包括：第一电压产生单元，用于通过第一电荷泵产生负电压; 以及用于通过第二电荷泵产生正电压的第二电压产生单元。在加速编程操作期间，第一电压产生单元使用外部电源电压提高第一电荷泵的泵送效率，并且第二电压产生单元直接输出外部电源电压。

39. 发明申请

US20060126387A1 Multi-level cell memory device and associated read method 有权
标题翻译：多级单元存储器件及相关读取方法
公开(公告)号：US20060126387A1
公开(公告)日：2006-06-15
申请号：US11296476
申请日：2005-12-08
申请人： Dae-Han Kim , Seung-Keun Lee
发明人： Dae-Han Kim , Seung-Keun Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/24
摘要： A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first magnitude to detect the value of a most significant bit (MSB) and generating the reference current with a second magnitude to detect the value of a least significant bit (LSB). The respective values of the MSB and the LSB are detected by comparing the first and second reference currents to an amount of current flowing through the memory cell during the read operation. The respective magnitudes of the first and second reference currents are determined by different reference voltages generated by a reference voltage generator.
摘要翻译： NOR闪存器件包括适于存储至少两位数据的存储器单元。通过产生具有第一幅度的参考电流来对存储器单元执行读取操作，以检测最高有效位（MSB）的值并产生具有第二幅度的参考电流以检测最低有效位（LSB）的值）。通过在读取操作期间将第一和第二参考电流与流过存储器单元的电流量进行比较来检测MSB和LSB的相应值。第一和第二参考电流的相应大小由参考电压发生器产生的不同参考电压确定。

40. 发明申请

US20060114738A1 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060114738A1
公开(公告)日：2006-06-01
申请号：US11327045
申请日：2006-01-06
申请人： Seung-Won Lee , Seung-Keun Lee
发明人： Seung-Won Lee , Seung-Keun Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/062 , G11C7/18 , G11C16/04 , G11C16/28 , G11C29/24 , G11C29/50004
摘要： A load of a main cell for applying a power to a sensing node of the main cell is equivalent to a load of a reference cell for applying a power to a sensing node of a reference cell. A high voltage higher than a power supply voltage is applied to gate ports of the main cell and the reference cell and is sensed to detect a degraded main cell. Thus, the reliability of a flash memory device is enhanced.
摘要翻译：用于向主单元的感测节点施加电力的主单元的负载等同于用于向参考单元的感测节点施加电力的参考单元的负载。将高于电源电压的高电压施加到主单元和参考单元的栅极端口，并且被感测以检测劣化的主单元。因此，提高了闪存装置的可靠性。

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