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    • 33. 发明申请
    • PYROGENICALLY PRODUCED SILICON DIOXIDE POWDER
    • 生产二氧化硅粉末
    • US20080145659A1
    • 2008-06-19
    • US12017861
    • 2008-01-22
    • Kai SCHUMACHERNaruyasu IshibashiHitoshi KobayashiPaul Brandl
    • Kai SCHUMACHERNaruyasu IshibashiHitoshi KobayashiPaul Brandl
    • C01B33/12
    • C01B33/183Y10T428/2982
    • Pyrogenically produced silicon dioxide powder in the form of aggregates of primary particles having a BET surface area of 300±25 m2/g, wherein the aggregates display an average surface area of 4800 to 6000 nm2, an average equivalent circle diameter (ECD) of 60 to 80 nm and an average circumference of 580 to 750 nm.It is produced by a pyrogenic process in which silicon tetrachloride and a maximum of up to 40 wt. % of a second silicon component comprising H3SiCl, H2SiCl2, HSiCl3, CH3SiCl3, (CH3)2SiCl2, (CH3)3SiCl and/or (n-C3H7)SiCl3 are mixed with primary air and a combustion gas and burnt into a reaction chamber, secondary air also being introduced into the reaction chamber, and the feed materials being chosen such that an adiabatic flame temperature of 1390 to 1450° C. is obtained.It can be used as a filler.
    • 以BET表面积为300±25m 2 / g的一次粒子的聚集体形式的热解生成的二氧化硅粉末,其中聚集体的平均表面积为4800〜6000nm, 2,平均当量圆直径(ECD)为60〜80nm,平均周长为580〜750nm。 它是通过热解法生产的,其中四氯化硅和最多达40wt。 %的包含H 3 SiCl,H 2 SiCl 2,HSiCl 3,CH,SUB的第二硅组分的% (CH 3)3 SiCl 3,(CH 3 3)2 SiCl 2,(CH 3) 3 N 3 SiCl 3和/或(n C 3 H 7)SiCl 3 3与 初级空气和燃烧气体并燃烧到反应室中,二次空气也被引入反应室,并且进料选择为使得绝热火焰温度为1390至1450℃。 它可以用作填料。
    • 38. 发明申请
    • Nonvolatile memory device and data write method for nonvolatile memory device
    • 非易失性存储器件和非易失性存储器件的数据写入方法
    • US20060023509A1
    • 2006-02-02
    • US11176324
    • 2005-07-08
    • Satoru KodairaHitoshi KobayashiKimihiro Maemura
    • Satoru KodairaHitoshi KobayashiKimihiro Maemura
    • G11C16/04
    • G11C16/0433
    • A nonvolatile memory device, wherein each of memory cells includes one of nonvolatile memory elements and one of wordline switches, wherein each of the wordlines connects in common gate electrodes of the wordline switches of memory cells arranged in the row direction; wherein each of the bitlines connects in common the wordline switches of memory cells arranged in the column direction; and wherein one of the first control gate lines connects in common control gate electrodes of the nonvolatile memory elements of M memory cells in one of memory cell blocks (M is an integer equal to or greater than 2); and wherein, when writing data into a desired memory cell, the wordline switches of the memory cells are turned ON by applying a wordline write voltage to a wordlines corresponding to the desired memory cell, a bitline write voltage is applied to the bitlines connected to the memory cells, and a control gate line write voltage is applied to one of the first control gate lines disposed in the memory cell block.
    • 一种非易失性存储器件,其中每个存储器单元包括非易失性存储器元件和字线开关中的一个,其中每个字线连接在沿行方向布置的存储器单元的字线开关的公共栅电极中; 其中每个位线共同地连接在列方向上布置的存储器单元的字线开关; 并且其中一个第一控制栅极线连接在存储单元块之一中的M个存储单元的非易失性存储元件的公共控制栅极中(M为等于或大于2的整数); 并且其中当将数据写入期望的存储单元时,通过将字线写入电压施加到对应于期望的存储单元的字线来使存储单元的字线切换为ON,位线写入电压被施加到连接到所述存储单元的位线 存储单元和控制栅线写入电压被施加到设置在存储单元块中的第一控制栅极线之一。
    • 39. 发明申请
    • Nonvolatile memory device
    • 非易失性存储器件
    • US20050275009A1
    • 2005-12-15
    • US11148302
    • 2005-06-09
    • Kimihiro MaemuraSatoru KodairaHitoshi Kobayashi
    • Kimihiro MaemuraSatoru KodairaHitoshi Kobayashi
    • H01L21/8247G11C16/04H01L21/28H01L27/115H01L29/423H01L29/76H01L29/788H01L29/792
    • H01L21/28273G11C16/0416G11C2216/10H01L27/115H01L27/11521H01L27/11558H01L29/42324H01L29/7883
    • A nonvolatile memory device includes: a semiconductor layer of a first conductivity type in which a first region, a second region, and a third region are partitioned by an isolation insulating layer; a semiconductor section of a second conductivity type provided in the first region and functioning as a control gate; a semiconductor section of the first conductivity type provided in the second region; a semiconductor section of the second conductivity type provided in the third region; an insulating layer provided on the semiconductor layer in the first to third regions; a floating gate electrode provided on the insulating layer across the first to third regions; impurity regions of the first conductivity type provided on each side of the floating gate electrode in the first region; impurity regions of the second conductivity type provided on each side of the floating gate electrode in the second region and functioning as either a source region or a drain region; and impurity regions of the first conductivity type provided on each side of the floating gate electrode in the third region and functioning as either a source region or a drain region.
    • 非易失性存储器件包括:第一导电类型的半导体层,其中第一区域,第二区域和第三区域被隔离绝缘层分隔; 第二导电类型的半导体部分,设置在第一区域中并用作控制栅极; 设置在第二区域中的第一导电类型的半导体部分; 设置在第三区域中的第二导电类型的半导体部分; 设置在第一至第三区域的半导体层上的绝缘层; 在第一至第三区域上设置在绝缘层上的浮栅电极; 设置在第一区域中的浮置栅电极的每一侧上的第一导电类型的杂质区域; 第二导电类型的杂质区域设置在第二区域中的浮置栅电极的每一侧上并且用作源极区域或漏极区域; 以及设置在第三区域中的浮栅的每一侧上的第一导电类型的杂质区,并且用作源区或漏区。