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31. 发明授权

US07053403B1 Iridium oxide nanostructure 有权
标题翻译：氧化铱纳米结构
公开(公告)号：US07053403B1
公开(公告)日：2006-05-30
申请号：US11339876
申请日：2006-01-26
申请人： Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff , Sheng Teng Hsu
发明人： Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff , Sheng Teng Hsu
IPC分类号： H01L29/10 , H01L29/12
CPC分类号： H01L21/31111 , B81C1/00111 , B82Y10/00
摘要： A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.
摘要翻译：提供了用于构图氧化铱（IrOx）纳米结构的方法。该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。例如，第一种材料可以是难熔金属或难熔金属氧化物。第二种材料可以是SiOx。选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。

32. 发明授权

US07022621B1 Iridium oxide nanostructure patterning 有权
标题翻译：氧化铱纳米结构图案
公开(公告)号：US07022621B1
公开(公告)日：2006-04-04
申请号：US11013804
申请日：2004-12-15
申请人： Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff , Sheng Teng Hsu
发明人： Fengyan Zhang , Gregory M. Stecker , Robert A. Barrowcliff , Sheng Teng Hsu
IPC分类号： H01L21/461
CPC分类号： H01L21/31111 , B81C1/00111 , B82Y10/00
摘要： A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.
摘要翻译：提供了用于构图氧化铱（IrOx）纳米结构的方法。该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。例如，第一种材料可以是难熔金属或难熔金属氧化物。第二种材料可以是SiOx。选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。

33. 发明授权

US06911361B2 Low temperature processing of PCMO thin film on Ir substrate for RRAM application 有权
标题翻译：用于RRAM应用的Ir衬底上的PCMO薄膜的低温处理
公开(公告)号：US06911361B2
公开(公告)日：2005-06-28
申请号：US10384846
申请日：2003-03-10
申请人： Fengyan Zhang , Wei-Wei Zhuang , Wei Pan , Sheng Teng Hsu
发明人： Fengyan Zhang , Wei-Wei Zhuang , Wei Pan , Sheng Teng Hsu
IPC分类号： H01L27/108 , G11C13/00 , H01L45/00 , H01L21/8242 , H01L21/31 , H01L21/469
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1608
摘要： A method of applying a PCMO thin film on an iridium substrate for use in a RRAM device, includes preparing a substrate; depositing a barrier layer on the substrate; depositing a layer of iridium on the barrier layer; spin coating a layer of PCMO on the iridium; baking the PCMO and substrate in a three-step baking process; post-bake annealing the substrate and the PCMO in a RTP chamber; repeating said spin coating, baking and annealing steps until the PCMO has a desired thickness; annealing the substrate and PCMO; depositing a top electrode; and completing the RRAM device.
摘要翻译：在用于RRAM器件的铱衬底上施加PCMO薄膜的方法包括制备衬底; 在衬底上沉积阻挡层; 在阻挡层上沉积一层铱; 在铱上旋涂一层PCMO; 在三步烘烤过程中烘烤PCMO和基材; 在RTP室中对基板和PCMO进行后烘烤退火; 重复所述旋涂，烘烤和退火步骤直到PCMO具有所需的厚度; 退火基板和PCMO; 沉积顶部电极; 并完成RRAM设备。

34. 发明授权

US06897074B1 Method for making single-phase c-axis doped PGO ferroelectric thin films 失效
标题翻译：制备单相c轴掺杂PGO铁电薄膜的方法
公开(公告)号：US06897074B1
公开(公告)日：2005-05-24
申请号：US10794736
申请日：2004-03-03
申请人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Teng Hsu
发明人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L21/00 , H01L21/02 , H01L21/316 , H01L41/22
CPC分类号： H01L21/31691 , H01L28/55 , H01L41/317
摘要： A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby-xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.
摘要翻译：描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括沉积在0.1N和0.5之间的掺杂前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。

35. 发明授权

US06833572B2 Electrode materials with improved hydrogen degradation resistance 失效
标题翻译：具有改善耐氢降解性的电极材料
公开(公告)号：US06833572B2
公开(公告)日：2004-12-21
申请号：US10229603
申请日：2002-08-27
申请人： Fengyan Zhang , Tingkai Li , Hong Ying , Yoshi Ono , Sheng Teng Hsu
发明人： Fengyan Zhang , Tingkai Li , Hong Ying , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2976
CPC分类号： H01L28/75 , H01L21/31604 , H01L21/31683 , H01L28/55
摘要： An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.
摘要翻译：用于铁电体器件的电极包括底部电极; 铁电层以及形成在强电介质层上并由金属组合形成的顶部电极，其包括从由铂和铱组成的金属组中的第一金属取得的金属和从由铝和钛组成的金属组中的第二金属; 其中所述顶部电极用作钝化层，并且其中所述顶部电极在氢气氛中的高温退火之后保持导电。在铁电体器件中形成耐氢电极的方法包括形成底电极; 在底部电极上形成铁电层; 在铁电层上沉积顶部电极; 包括同时从由铂和铱组成的金属组中取出的第一金属; 和从由铝和钛组成的金属组中获取的第二金属; 以及通过在氧气氛中对所述结构退火以在所述顶部电极上形成氧化物钝化层来形成钝化层。

36. 发明授权

US06537361B2 Method of the synthesis and control of PGO spin-coating precursor solutions 失效
公开(公告)号：US06537361B2
公开(公告)日：2003-03-25
申请号：US09822637
申请日：2001-03-30
申请人： Wei-Wei Zhuang , Fengyan Zhang , Jer-Shen Maa , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , Fengyan Zhang , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L2122
CPC分类号： H01L21/02197 , C01G21/00 , C01P2002/86 , H01L21/02112 , H01L21/02175 , H01L21/02282 , H01L21/31604 , H01L21/31691
摘要： A method of synthesizing a PGO spin-coating precursor solution includes utilizing the starting materials of lead acetate trihydrate (Pb(OAc)2•3H2O) and germanium alkoxide (Ge(OR)4(R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol) ethyl ether. The mixed solution of lead and di(ethylene glycol) ethyl ether is heated in an atmosphere of air at a temperature no greater than 185° C., and preferably no greater than 190° C. for a time period in a range of thirty minutes to four hours. During the heating step the color of the solution is monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol) ethyl ether to make the PGO spin-coating solution. This second step also entails heating the solution to a temperature no greater than 190° C. for a time period in a range of 0.5 to 2.0 hours. The process results in a PGO precursor solution suitable for use in spin-coating.

37. 发明授权

US06410346B1 Method of forming ferroelastic lead germanate thin films 有权
标题翻译：形成铁弹性锗酸铅薄膜的方法
公开(公告)号：US06410346B1
公开(公告)日：2002-06-25
申请号：US10010186
申请日：2001-12-06
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L21/02197 , C23C16/40 , H01L21/02271 , H01L21/31604 , H01L21/31691
摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.
摘要翻译：提供Pb3GeO5相PGO薄膜。该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。该方法在溶剂中混合Pd和锗。将溶液加热以形成分解的前体蒸汽。该方法提供沉积温度和压力。沉积的膜也被退火以增强膜的铁弹性特征。还提供了由本发明PGO膜制成的铁弹性电容器。

38. 发明申请

US20090011536A1 OPTICAL DEVICE WITH IROX NANOSTRUTURE ELECTRODE NEURAL INTERFACE 失效
标题翻译：光学器件与IROX纳米电极神经接口
公开(公告)号：US20090011536A1
公开(公告)日：2009-01-08
申请号：US11496157
申请日：2006-07-31
申请人： Fengyan Zhang , Sheng Teng Hsu
发明人： Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： C30B25/00 , A61N1/0543 , B82Y5/00 , B82Y10/00 , B82Y30/00 , C30B29/16 , C30B29/605 , Y10S977/811 , Y10S977/904 , Y10S977/932
摘要： An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x≦4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.
摘要翻译：提供了具有氧化铱（IrOx）电极神经接口的光学器件及相应的制造方法。该方法提供了一个衬底并且形成了覆盖衬底的第一导电电极。具有第一电接口的光电器件连接到第一电极。光电器件的第二电接口连接到形成在光伏器件上的第二导电电极。形成了覆盖第二电极的神经界面单晶IrOx纳米结构阵列，其中x <= 4。 IrOx纳米结构可以部分地涂覆有诸如SiO 2，SiN，TiO 2或旋转玻璃（SOG）之类的电绝缘体，使得IrOx远端暴露。在一个方面，为了定向IrOx纳米结构的生长方向，形成了由诸如LiNbO 3，LiTaO 3或SA的材料制成的第二电极表面上的缓冲层。

39. 发明授权

US07438759B2 Ambient environment nanowire sensor 失效
公开(公告)号：US07438759B2
公开(公告)日：2008-10-21
申请号：US11264113
申请日：2005-11-01
申请人： Fengyan Zhang , Robert A. Barrowcliff , Jong-Jan Lee , Sheng Teng Hsu
发明人： Fengyan Zhang , Robert A. Barrowcliff , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： C30B1/02
CPC分类号： B81C1/00182 , B81B2201/0214 , Y10S977/712 , Y10S977/762
摘要： An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.

40. 发明申请

US20080157354A1 Multiple stacked nanostructure arrays and methods for making the same 审中-公开
标题翻译：多层叠纳米结构阵列及其制造方法
公开(公告)号：US20080157354A1
公开(公告)日：2008-07-03
申请号：US11649523
申请日：2007-01-03
申请人： Fengyan Zhang , Sheng Teng Hsu
发明人： Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L27/00 , H01L21/02
CPC分类号： H01L29/0665 , B82Y10/00 , G01N27/127 , H01L29/0673 , H01L29/0676 , H01L31/03529 , Y02E10/50
摘要： A method of fabricating a stacked nanostructure array includes preparing a substrate; forming a bottom electrode directly on the substrate; growing a first nanostructure array directly on the bottom electrode; forming an insulating layer on the first nanostructure array; exposing the upper surface of the first nanostructure array; depositing a second, and subsequent, nanostructure array on a nanostructure array immediately below the second and subsequent nanostructure array; repeating said forming, said exposing and said depositing a subsequent steps to form a stacked nanostructure array; removing an uppermost insulating layer; and forming a top electrode on an uppermost nanostructure array. A sensor incorporating the nanostructure array includes top and bottom electrodes with plural layers of nanostructure array therebetween.
摘要翻译：一种叠层纳米结构阵列的制造方法包括：制备衬底; 直接在基板上形成底部电极; 直接在底部电极上生长第一个纳米结构阵列; 在所述第一纳米结构阵列上形成绝缘层; 暴露第一纳米结构阵列的上表面; 在第二和随后的纳米结构阵列正下方的纳米结构阵列上沉积第二和随后的纳米结构阵列; 重复所述形成，所述曝光和沉积随后的步骤以形成堆叠的纳米结构阵列; 去除最上层绝缘层; 并在最上面的纳米结构阵列上形成顶部电极。结合纳米结构阵列的传感器包括其间具有多层纳米结构阵列的顶部和底部电极。

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