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31. 发明授权

US06847550B2 Nonvolatile semiconductor memory having three-level memory cells and program and read mapping circuits therefor 有权
标题翻译：具有三电平存储器单元的非易失性半导体存储器及其编程和读取映射电路
公开(公告)号：US06847550B2
公开(公告)日：2005-01-25
申请号：US10280939
申请日：2002-10-25
申请人： Eungjoon Park
发明人： Eungjoon Park
IPC分类号： G11C11/56 , G11C16/26 , G11C16/04
CPC分类号： G11C16/26 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C2211/5641
摘要： A memory uses multiple threshold levels in a memory cell that are not a power of two, and further uses a cell mapping technique wherein the read mapping is only a partial function The domain of read states for a single three-level memory cell, for example, has three states, but only two of them can be uniquely mapped to a bit. The domain of read states for two three-level memory cell, for example, has nine states, but only eight of them can be uniquely mapped to three bits. Although the read mapping is only partial, the voltage margin for the three-level memory cells is larger that the voltage margin available in the commonly used four-level memory cells. This increased voltage margin facilitates memory cell threshold voltage sensing, thereby increasing the reliability of the memory. Memory reliability may be further improved by increasing the voltage margin between the memory cell 0 state and the 1 state relative to the voltage margin between the 1 state and the 2 state, which more effectively accommodates charge loss from the 0 state through electron leakage. Asymmetrical read and program mapping may also be used to improve read reliability in the presence of ground noise or VCC noise.
摘要翻译：存储器在不是2的幂的存储器单元中使用多个阈值电平，并且还使用单元映射技术，其中读取映射仅是部分功能。例如，单个三电平存储器单元的读取状态域，有三个状态，但只有两个可以被唯一地映射到一点。例如，两个三电平存储单元的读状态域有九个状态，但只有八个可以唯一地映射到三位。虽然读取映射仅仅是部分的，但三电平存储单元的电压裕度大于常用四电平存储单元中可用的电压余量。这种增加的电压裕度便于存储单元阈值电压感测，从而增加存储器的可靠性。通过相对于1状态和2状态之间的电压裕度增加存储单元0状态和1状态之间的电压裕度可以进一步提高存储器可靠性，这更有效地适应从0状态通过电子泄漏的电荷损失。不对称读取和程序映射也可用于在存在接地噪声或VCC噪声的情况下提高读取可靠性。

32. 发明授权

US06771541B1 Method and apparatus for providing row redundancy in nonvolatile semiconductor memory 有权
标题翻译：在非易失性半导体存储器中提供行冗余的方法和装置
公开(公告)号：US06771541B1
公开(公告)日：2004-08-03
申请号：US10375556
申请日：2003-02-25
申请人： Eungjoon Park
发明人： Eungjoon Park
IPC分类号： G11C1606
CPC分类号： G11C29/82 , G11C16/08 , G11C16/3404
摘要： In a NOR-type flash memory of either the ETOX or virtual ground type that is programmed using electron injection and erased using FN tunneling, and that has row redundancy, the typical sequence of operations used for an embedded sector erase, namely the Preprogram, Preprogram Verify, Erase, Erase Verify, Post-Program Verify, and Post-Program operations, need not be performed for the data cells on bad or shorted rows or in unused redundant rows. Instead, the bad or shorted rows or the unused redundant rows are suitably biased so that the threshold voltages of the data cells in these rows tend to converge to a threshold voltage near the UV erased threshold.
摘要翻译：在使用电子注入并使用FN隧道擦除并具有行冗余度的ETOX或虚拟接地类型的NOR型闪存中，用于嵌入式扇区擦除的典型操作序列，即Preprogram，Preprogram 不需要对不良或短路行或未使用的冗余行中的数据单元执行验证，擦除，擦除验证，程序后验证和后期编程操作。相反，不良或短路行或未使用的冗余行被适当地偏置，使得这些行中的数据单元的阈值电压倾向于收敛到UV擦除阈值附近的阈值电压。

33. 发明授权

US06416556B1 Structure and method of operating an array of non-volatile memory cells with source-side programming 有权
标题翻译：使用源端编程操作非易失性存储单元阵列的结构和方法
公开(公告)号：US06416556B1
公开(公告)日：2002-07-09
申请号：US09757088
申请日：2001-01-08
申请人： Eungjoon Park
发明人： Eungjoon Park
IPC分类号： G11C1134
CPC分类号： G11C16/0416
摘要： An array of non-volatile memory cells are arranged along rows and columns. Each memory cell has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further includes a stack of floating gate and select gate extending over the channel region. The select gate of the cells along each row are connected together to form a wordline. Each of a number of data lines is coupled to the drain regions of at least a portion of a column of cells. Each of a number of source lines is coupled to a source region of a plurality of cells along at least a portion of a row of cells. In such a memory array, a selected memory cell is biased so that a threshold voltage of the selected memory cell is increased by injection of hot electrons from a portion of the channel region near the source region to the floating gate.
摘要翻译：一系列非易失性存储单元沿行和列排列。每个存储单元具有与源极间隔开的漏极区域，以在它们之间形成沟道区域。漏区具有比源区更深的深度。每个存储器单元进一步包括在沟道区域上延伸的浮置栅极和选择栅极的堆叠。沿着每行的单元格的选择栅极连接在一起形成字线。多条数据线中的每一条耦合到一列单元的至少一部分的漏极区。多个源极线中的每一个沿着一行单元的至少一部分耦合到多个单元的源极区域。在这种存储器阵列中，选择的存储单元被偏置，使得通过从源极区域附近的沟道区域的一部分注入到浮动栅极来增加所选存储单元的阈值电压。

34. 发明授权

US06288938B1 Flash memory architecture and method of operation 有权
标题翻译：闪存架构和操作方法
公开(公告)号：US06288938B1
公开(公告)日：2001-09-11
申请号：US09433245
申请日：1999-11-03
申请人： Eungjoon Park , Ali Pourkeramati
发明人： Eungjoon Park , Ali Pourkeramati
IPC分类号： G11C1400
CPC分类号： G11C16/0416 , H01L29/7886
摘要： A flash memory device and its method of operation provide for selective, e.g., bit-by-bit, erase operation resulting in much narrower distribution for erase threshold voltage VTE. Latches that couple to the array are set or reset depending on cell content during erase verify. The output of the latches are then applied to selected cells to perform erase. The flash architecture allows for bit-by-bit erase verify operation resulting in a tighter VTE distribution and elimination of the need for preprogramming. In a preferred embodiment, the flash cell is programmed by CHE tunneling and erased by FN tunneling both occurring on the same side (e.g., drain side) of the cell transistor.
摘要翻译：闪速存储器件及其操作方法提供了选择性的，例如逐位的擦除操作，导致擦除阈值电压VTE的分布更窄。耦合到阵列的锁存器根据擦除验证期间的单元格内容设置或复位。然后将锁存器的输出应用于选定的单元进行擦除。闪存架构允许逐位擦除验证操作，导致更紧密的VTE分发和消除对预编程的需要。在优选实施例中，闪存单元通过CHE隧道编程，并通过发生在单元晶体管的同一侧（例如，漏极侧）上的FN隧道擦除。

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