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31. 发明授权

US07511302B2 TFT array panel 失效
标题翻译： TFT阵列面板
公开(公告)号：US07511302B2
公开(公告)日：2009-03-31
申请号：US11049742
申请日：2005-02-04
申请人： Je-Hun Lee , Jae-Kyeong Lee , Chang-Oh Jeong , Beom-Seok Cho
发明人： Je-Hun Lee , Jae-Kyeong Lee , Chang-Oh Jeong , Beom-Seok Cho
IPC分类号： H01L27/14
CPC分类号： H01L29/66765 , H01L27/12 , H01L29/458 , H01L29/4908
摘要： Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).
摘要翻译：在含有至少一个氧，氮和碳的前体气体的存在下，在基板上沉积钼以形成钼层，形成用于较大平板显示器的多层布线。铝层沉积在钼层上。可以在铝层上形成另一金属层。钼层具有面心立方（FCC）晶格结构，其优选取向为（111）。

32. 发明申请

US20070289769A1 MULTI-LAYER WIRING, METHOD OF MANUFACTURING THE SAME AND THIN FILM TRANSISTOR HAVING THE SAME 审中-公开
标题翻译：多层布线及其制造方法及其薄膜薄膜晶体管
公开(公告)号：US20070289769A1
公开(公告)日：2007-12-20
申请号：US11844164
申请日：2007-08-23
申请人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Yang-Ho Bae
发明人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Yang-Ho Bae
IPC分类号： H01B5/00
CPC分类号： H01L27/12 , H01L21/76838 , H01L23/5283 , H01L23/53209 , H01L29/4908 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A multi-layer wiring for use with thin film transistors (TFTs), methods of manufacturing the multi-layer wiring, and TFTs employing the multi-layer wiring are provided. In one embodiment, the multi-layer wiring includes a main wiring and a sub-wiring on the main wiring. The main wiring includes a first metal and the sub-wiring includes an alloy wherein a majority of the alloy is the first metal. The multi-layer wiring can exhibit decreased electrical resistance and a reduced tendency to develop malfunctions such as hillocks or spiking. The multi-layer wiring can also exhibit improved contact characteristics with other conductive elements of TFT display devices.
摘要翻译：提供了用于薄膜晶体管（TFT）的多层布线，多层布线的制造方法以及采用多层布线的TFT。在一个实施例中，多层布线包括主布线和主布线上的副布线。主配线包括第一金属，并且子布线包括其中大部分合金是第一金属的合金。多层布线可以表现出降低的电阻和降低发展故障的倾向，如小丘或尖峰。多层布线也可以表现出与TFT显示装置的其它导电元件的接触特性的改善。

33. 发明授权

US07301170B2 Thin film transistor array panel and method for manufacturing the same 失效
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07301170B2
公开(公告)日：2007-11-27
申请号：US11180989
申请日：2005-07-12
申请人： Beom-Seok Cho , Yang-Ho Bae , Je-Hun Lee , Chang-Oh Jeong
发明人： Beom-Seok Cho , Yang-Ho Bae , Je-Hun Lee , Chang-Oh Jeong
IPC分类号： H01L29/04
CPC分类号： G02F1/136286 , G02F2001/13629 , G02F2001/136295 , H01L27/3276 , Y10S438/924
摘要： The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.
摘要翻译：本发明提供一种TFT阵列面板及其制造方法，其特征在于，具有含有Al的金属的下层和包含钼（Mo）的钼合金（Mo合金）的上层的信号线，至少包括铌（Nb），钒（V）和钛（Ti）之一。因此，防止在蚀刻工艺中可能出现的底切，突出和小鼠咬合，并且提供具有低电阻率和良好接触特性的信号线的TFT阵列面板。

34. 发明申请

US20070102770A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20070102770A1
公开(公告)日：2007-05-10
申请号：US11619451
申请日：2007-01-03
申请人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
发明人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
IPC分类号： H01L29/76
CPC分类号： H01L27/1288 , G02F2001/136236 , H01L21/31144 , H01L21/32139 , H01L27/1214 , H01L27/124 , H01L29/41733
摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.
摘要翻译：一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

35. 发明申请

US20060091396A1 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060091396A1
公开(公告)日：2006-05-04
申请号：US11249500
申请日：2005-10-14
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L29/04
CPC分类号： H01L27/3279 , H01L27/124 , H01L27/1288 , H01L51/0023 , H01L51/56
摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.
摘要翻译：本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

36. 发明申请

US20060076562A1 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060076562A1
公开(公告)日：2006-04-13
申请号：US11215067
申请日：2005-08-29
申请人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
发明人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
IPC分类号： H01L29/04 , H01L27/148
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/12 , H01L29/458
摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode at on the gate electrode; and a pixel electrode electrically connected to the drain electrode.
摘要翻译：本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地与扩散阻挡层接触并且与栅电极上的源电极相对; 以及电连接到漏电极的像素电极。

37. 发明申请

US20050221546A1 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20050221546A1
公开(公告)日：2005-10-06
申请号：US11082967
申请日：2005-03-18
申请人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
发明人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
IPC分类号： G02F1/1368 , G09F9/30 , G09G3/36 , G09G3/38 , H01L21/00 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L27/1288 , G02F2001/136236 , H01L21/31144 , H01L21/32139 , H01L27/1214 , H01L27/124 , H01L29/41733
摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.
摘要翻译：一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

38. 发明授权

US08455277B2 Thin film transistor array panel and manufacturing method thereof 失效
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08455277B2
公开(公告)日：2013-06-04
申请号：US13523767
申请日：2012-06-14
申请人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L21/84
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a plurality of gate lines, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括多个栅极线，多个公共电极，覆盖栅极线和公共电极的栅极绝缘层，形成在栅极绝缘层上的多个半导体层，多个包括多个源电极并形成在半导体层上的数据线，形成在半导体层上的多个漏电极以及与公共电极重叠并连接到漏电极的多个像素电极。由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生不透明金属Sn或Zn。

39. 发明授权

US08372701B2 Thin film transistor array panel including layered line structure and method for manufacturing the same 有权
公开(公告)号：US08372701B2
公开(公告)日：2013-02-12
申请号：US12576217
申请日：2009-10-08
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L21/00
CPC分类号： H01L27/1214 , H01L27/1225 , H01L27/124
摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

40. 发明授权

US08288771B2 Thin film transistor array panel and manufacturing method thereof 有权
公开(公告)号：US08288771B2
公开(公告)日：2012-10-16
申请号：US13204553
申请日：2011-08-05
申请人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L29/786 , H01L21/336 , H01L21/84
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the metal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

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