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31. 发明授权

US07456047B2 Thermally enhanced electronic flip-chip packaging with external-connector-side die and method 有权
标题翻译：具有外部连接器侧芯片的热增强型电子倒装芯片封装和方法
公开(公告)号：US07456047B2
公开(公告)日：2008-11-25
申请号：US11839120
申请日：2007-08-15
申请人： Debendra Mallik , Robert L. Sankman
发明人： Debendra Mallik , Robert L. Sankman
IPC分类号： H01L21/50
CPC分类号： H05K1/0204 , H01L23/13 , H01L23/36 , H01L23/4006 , H01L23/49816 , H01L25/0655 , H01L2224/16225 , H01L2224/73253 , H01L2924/00014 , H01L2924/01078 , H01L2924/01087 , H01L2924/10253 , H01L2924/15151 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H05K1/182 , H05K2201/09054 , H05K2201/1056 , H05K2201/10734 , Y10T29/49124 , H01L2924/00 , H01L2224/0401
摘要： A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to be a surface for connection to a heat sink. One or more chips are bonded to the wiring layer, and an array of connectors, such as solder balls are provided around the periphery of the chip(s) for connection to a printed circuit board. In some embodiments, the printed circuit board has a hole that the chip(s) extend into to allow smaller external-connection solder balls. In some embodiments, a second heat sink is connected to the back of the chip through the PCB hole.
摘要翻译：一种用于制造具有改善的热传导特性和高频响应的封装的方法和装置。诸如铜的相对厚的封装衬底具有结合到一个面的布线层，使相对的面露出，例如是用于连接到散热器的表面。将一个或多个芯片接合到布线层，并且在芯片的周边周围设置连接器阵列（例如焊球），以连接到印刷电路板。在一些实施例中，印刷电路板具有一个孔，芯片延伸进入以允许更小的外部连接焊球。在一些实施例中，第二散热器通过PCB孔连接到芯片的背面。

32. 发明授权

US07187068B2 Methods and apparatuses for providing stacked-die devices 有权
标题翻译：用于提供堆叠式模具的方法和设备
公开(公告)号：US07187068B2
公开(公告)日：2007-03-06
申请号：US10917142
申请日：2004-08-11
申请人： Daewoong Suh , Debendra Mallik
发明人： Daewoong Suh , Debendra Mallik
IPC分类号： H01L23/02 , H01L23/48
CPC分类号： H01L23/3128 , H01L23/49816 , H01L24/48 , H01L25/105 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and associated wires are protected by an encapsulant leaving an upper portion of each interconnection exposed. For one embodiment of the invention the encapsulant is a stencil-printable encapsulant and the upper portion of the interconnection is exposed by use of a patterned stencil during application of the encapsulant.
摘要翻译：提供由堆叠的子包装组成的堆叠管芯装置的方法和装置。对于本发明的一个实施例，每个子封装具有形成在衬底的裸片侧上的互连，用于互连到另一个子封装。模具和相关电线由密封剂保护，留下每个互连的上部部分。对于本发明的一个实施例，密封剂是模版印刷的密封剂，并且在施加密封剂期间通过使用图案化的模板来暴露互连的上部。

33. 发明授权

US06975025B2 Semiconductor chip package and method of manufacturing same 失效
标题翻译：半导体芯片封装及其制造方法
公开(公告)号：US06975025B2
公开(公告)日：2005-12-13
申请号：US09999169
申请日：2001-12-03
申请人： Vassoudevane LeBonheur , Debendra Mallik , Eduardo J. Bolanos
发明人： Vassoudevane LeBonheur , Debendra Mallik , Eduardo J. Bolanos
IPC分类号： H01L21/56 , H01L23/13 , H01L23/498 , H01L25/065 , H01L23/053
CPC分类号： H01L23/13 , H01L21/563 , H01L23/49816 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/16 , H01L2224/05599 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/49175 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/83051 , H01L2224/854 , H01L2225/0651 , H01L2225/06517 , H01L2225/06568 , H01L2225/06589 , H01L2924/00014 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15312 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A semiconductor chip package, an electronic system, and a method of manufacturing such package. A lower structure includes a lower insulating layer and a metal layer made of separate electrical conductors. A wall defines a cavity on the metal layer. Electrical conductors extend from the metal layer to contact points elsewhere in the semiconductor chip package. Conductor members are positioned on the electrical conductors of the metal layer. A semiconductor chip is positioned on the conductor members within the cavity, with an isolation area between the semiconductor chip and the wall. The electrical contacts on the semiconductor chip contact the conductor members to couple the semiconductor chip to the contact points. Underfill material is provided within the isolation area between the perimeter surface and the wall, and is prevented by the wall from spreading to other areas. Placement of the semiconductor chip within the cavity reduces the package thickness.
摘要翻译：半导体芯片封装，电子系统和制造这种封装的方法。下部结构包括下绝缘层和由分开的电导体制成的金属层。壁在金属层上限定一个空腔。电导体从金属层延伸到半导体芯片封装中别处的接触点。导体构件位于金属层的电导体上。半导体芯片位于腔内的导体部件上，半导体芯片与壁之间具有隔离区域。半导体芯片上的电触点与导体部件接触，将半导体芯片连接到接触点。底部填充材料设置在周边表面和壁之间的隔离区域内，并且被壁阻止扩散到其它区域。半导体芯片在腔内的放置减小了封装厚度。

34. 发明申请

US20050127489A1 Microelectronic device signal transmission by way of a lid 审中-公开
标题翻译：微电子器件信号通过盖子传输
公开(公告)号：US20050127489A1
公开(公告)日：2005-06-16
申请号：US10733183
申请日：2003-12-10
申请人： Debendra Mallik , Chris Baldwin , Brent Stone
发明人： Debendra Mallik , Chris Baldwin , Brent Stone
IPC分类号： H01L21/48 , H01L21/60 , H01L23/02 , H01L23/04 , H01L23/36 , H01L23/492 , H01L23/498
CPC分类号： H01L23/492 , H01L23/04 , H01L23/36 , H01L23/49833 , H01L24/81 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15165 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/16195 , H01L2924/19041 , H01L2924/19043 , H01L2924/19106 , H01L2924/00015 , H01L2924/00 , H01L2224/05599
摘要： A microelectronic device package including an electrically conductive lid having an attachment surface, a substrate having an attachment surface, at least one interconnect extending between the lid attachment surface and the substrate attachment surface, at least one microelectronic die disposed between the lid attachment surface and the substrate attachment surface, and the substrate having at least one first conductive trace extending between the electrically conductive first interconnect and the microelectronic die. The microelectronic device package allows for the use of the electrically conductive lid as a path for conducting signals (preferably power or ground) to and/or from a microelectronic die.
摘要翻译：一种微电子器件封装，其包括具有附接表面的导电盖，具有附接表面的基底，在所述盖附接表面和所述基板附接表面之间延伸的至少一个互连件，设置在所述盖附接表面和所述盖附接表面之间的至少一个微电子管芯衬底附着表面，以及具有在导电的第一互连和微电子管芯之间延伸的至少一个第一导电迹线的衬底。微电子器件封装允许使用导电盖作为用于向微电子管芯和/或从微电子管芯传导信号（优选功率或接地）的路径。

35. 发明授权

US5519580A Method of controlling solder ball size of BGA IC components 失效
标题翻译：控制BGA IC元件焊球尺寸的方法
公开(公告)号：US5519580A
公开(公告)日：1996-05-21
申请号：US303440
申请日：1994-09-09
申请人： Siva Natarajan , Debendra Mallik
发明人： Siva Natarajan , Debendra Mallik
IPC分类号： H01L23/498 , H05K1/02 , H05K1/11 , H05K3/34 , H05K7/02
CPC分类号： H05K3/3436 , H01L23/49816 , H05K1/111 , H05K1/114 , H01L2924/0002 , H05K1/0201 , H05K2201/062 , H05K2201/09381 , H05K2201/0989 , H05K2201/10734 , H05K2201/10969 , H05K3/3452 , Y02P70/611 , Y02P70/613
摘要： A ball grid array (BGA) package which has a plurality of solder balls attached to solder landings that each have a number of tabs which extend from a center area of the landing. The tabs assist in a symmetric formation of solder balls that are formed on the landings. When constructing the package, a solder mask is applied to a bottom package surface before the application of the solder balls. The solder mask has a plurality of openings which expose the solder landings and are larger than the center area of the landings. Solder balls are then placed onto the solder landings and reflowed so that the balls become attached to the landings. The fully exposed center areas of the solder landings allow the solder to flow vertically along the outer walls of the landings, thereby providing a more robust solder joint. The exposed solder landings also allow a solder flux to be thoroughly cleaned after the solder balls are attached to the landings. Additionally, the land tabs insure an even solder flow about the solder landings to produce a symmetric uniform solder balls.
摘要翻译：一种球栅阵列（BGA）封装，其具有附接到焊接着陆点的多个焊球，每个焊球均具有从层站的中心区域延伸的多个突片。凸片有助于形成在平台上的焊球对称地形成。当构造封装时，在施加焊球之前，将焊接掩模施加到底部封装表面。焊接掩模具有多个露出焊接着陆的开口，并且大于平台的中心区域。然后将焊球放置在焊接层上并回流，使得球附着到平台上。焊接着陆的完全暴露的中心区域允许焊料沿着平台的外壁垂直流动，从而提供更坚固的焊点。暴露的焊接着陆还允许在焊球附接到着陆点之后彻底清洁焊剂。另外，焊盘可以确保焊料平齐地焊接在焊盘上，以产生对称均匀的焊球。

36. 发明申请

US20200098727A1 STACKED WIRE-BOND DICE ATTACHED BY PILLARS OR BUMPS ABOVE A FLIP-CHIP DIE ON A SEMICONDUCTOR PACKAGE SUBSTRATE 审中-公开
公开(公告)号：US20200098727A1
公开(公告)日：2020-03-26
申请号：US16141415
申请日：2018-09-25
申请人： Debendra Mallik , Robert L. Sankman , Sanka Ganesan , George Vakanas , Omkar Karhade , Sri Chaitra Jyotsna Chavali , Zhaozhi George Li , Holly A. Sawyer
发明人： Debendra Mallik , Robert L. Sankman , Sanka Ganesan , George Vakanas , Omkar Karhade , Sri Chaitra Jyotsna Chavali , Zhaozhi George Li , Holly A. Sawyer
IPC分类号： H01L25/065 , H01L25/00 , H01L23/00 , H01L23/538
摘要： A wire-bond memory die is coupled to a system-on-chip processor where the processor is flip-chip mounted on a semiconductor package substrate, and the wire-bond memory die is also flip-chip configured through a redistribution layer that pins out to a series of pillars that contact the semiconductor package substrate. The wire-bond memory die is stacked on the processor and the redistribution layer overhangs the processor to contact the series of pillars.

37. 发明授权

US09526285B2 Flexible computing fabric 有权
标题翻译：灵活计算架构
公开(公告)号：US09526285B2
公开(公告)日：2016-12-27
申请号：US13717909
申请日：2012-12-18
申请人： Aleksandar Aleksov , Ravindranath V. Mahajan , Sairam Agraharam , Ian A. Young , John C. Johnson , Debendra Mallik , John S. Guzek
发明人： Aleksandar Aleksov , Ravindranath V. Mahajan , Sairam Agraharam , Ian A. Young , John C. Johnson , Debendra Mallik , John S. Guzek
IPC分类号： H05K1/02 , H05K3/30 , A41D31/00 , H05K1/03 , H05K1/18 , H05K3/32 , H05K3/34
CPC分类号： A41D31/00 , H05K1/0274 , H05K1/038 , H05K1/188 , H05K3/323 , H05K3/3436 , Y10T29/4913
摘要： A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa.
摘要翻译：一种灵活的计算结构及其形成方法。柔性计算结构包括包括一个或多个通道并且包括至少两个端部的电子基板。至少一个计算元件安装在两端之间的电子基板上，并且至少一个功能元件安装在两端之间的电子基板上。通道形成元件之间的互连。此外，电子基板是柔性的并且具有在0.1GPa至30GPa范围内的挠曲模量。

38. 发明申请

US20160268231A1 METHODS TO FORM HIGH DENSITY THROUGH-MOLD INTERCONNECTIONS 有权
标题翻译：形成高密度通过模具互连的方法
公开(公告)号：US20160268231A1
公开(公告)日：2016-09-15
申请号：US14767471
申请日：2014-09-15
申请人： Omkar G. Karhade , Nitin A. Deshpande , Edvin Cetegen , Eric J. Li , Debendra Mallik , Bassam M. Ziadeh
发明人： Omkar G. Karhade , Nitin A. Deshpande , Edvin Cetegen , Eric J. Li , Debendra Mallik , Bassam M. Ziadeh
IPC分类号： H01L25/065 , H01L23/31 , H01L25/00 , H01L23/00 , H01L21/56 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/565 , H01L21/76802 , H01L21/76877 , H01L23/3142 , H01L23/49811 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/1329 , H01L2224/133 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/81201 , H01L2224/81203 , H01L2224/81205 , H01L2224/81207 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125 , H01L2225/06517 , H01L2225/06548 , H01L2225/1023 , H01L2225/1058 , H01L2924/01028 , H01L2924/01047 , H01L2924/01079 , H01L2924/01322 , H01L2924/0133 , H01L2924/014 , H01L2924/1433 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/1579 , H01L2924/1815 , H01L2924/01082 , H01L2924/0105 , H01L2924/00012 , H01L2924/01083 , H01L2924/01029 , H01L2924/00014 , H01L2924/0665
摘要： Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.
摘要翻译：制造微电子器件的方法包括形成具有多个微电子器件附着接合焊盘的微电子衬底和在其有效表面上和/或其有效表面上形成的至少一个互连接合焊盘，将微电子器件连接到多个微电子器件附接接合焊盘形成具有模具主体和至少一个从所述模具主体延伸的突起的模具追踪器，其中所述至少一个突出部包括至少一个侧壁和接触表面，所述至少一个突出部将所述模具追踪投影接触表面接触到相应的微电子衬底互连接合在微电子基板和模具追逐之间设置模具材料，并且通过从模具材料的顶表面延伸到相应的微电子衬底互连接合垫，去除模具追逐以形成至少一个互连。

39. 发明授权

US09099444B2 3D integrated circuit package with through-mold first level interconnects 有权
标题翻译： 3D集成电路封装，具有通用模具一级互连
公开(公告)号：US09099444B2
公开(公告)日：2015-08-04
申请号：US13995778
申请日：2011-12-22
申请人： Debendra Mallik , Robert L. Sankman
发明人： Debendra Mallik , Robert L. Sankman
IPC分类号： H01L23/02 , H01L23/48 , H01L23/31 , H01L25/065 , H01L23/00 , H01L25/00 , H01L21/56
CPC分类号： H01L25/0657 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/82 , H01L23/3114 , H01L23/3135 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/051 , H01L2224/05147 , H01L2224/05541 , H01L2224/05571 , H01L2224/056 , H01L2224/05647 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/141 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16265 , H01L2224/1703 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81986 , H01L2224/9202 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2225/06582 , H01L2924/00014 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/12042 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1461 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2224/81 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/05552 , H01L2924/01079 , H01L2224/11
摘要： 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.
摘要翻译：描述了具有通过模具一级互连的3D集成电路封装以及形成这种封装的方法。例如，半导体封装包括衬底。底部半导体管芯具有表面积的活性侧。底部半导体管芯与主体侧远离衬底耦合到衬底。顶部半导体管芯具有活性侧，其表面积大于底部半导体管芯的表面积。顶部半导体管芯耦合到衬底，其中有源侧靠近衬底。底部半导体管芯的有源侧面向并导电耦合到顶部半导体管芯的有源侧。顶部半导体管芯通过旁路底部半导体管芯的一级互连导体耦合到衬底。

40. 发明申请

US20150171065A1 EMBEDDED MEMORY AND POWER MANAGEMENT SUBPACKAGE 有权
标题翻译：嵌入式存储器和电源管理单元
公开(公告)号：US20150171065A1
公开(公告)日：2015-06-18
申请号：US14104877
申请日：2013-12-12
申请人： John S. Guzek , Debendra Mallik , Sasha N. Oster , Timothy E. McIntosh
发明人： John S. Guzek , Debendra Mallik , Sasha N. Oster , Timothy E. McIntosh
IPC分类号： H01L25/18 , H01L23/48 , H01L21/56 , H01L23/00 , H01L25/00 , H01L23/31
CPC分类号： H01L25/18 , H01L23/3128 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L23/5389 , H01L24/17 , H01L24/19 , H01L24/20 , H01L25/0652 , H01L25/50 , H01L2224/12105 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/2518 , H01L2224/73253 , H01L2224/73259 , H01L2225/06513 , H01L2225/06517 , H01L2225/06548 , H01L2225/06562 , H01L2225/06589 , H01L2924/1205 , H01L2924/1206 , H01L2924/1427 , H01L2924/1432 , H01L2924/1434 , H01L2924/15321 , H01L2924/16251 , H01L2924/182
摘要： Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了允许诸如处理器和存储器的设备之间的相对短的连接的集成电路封装组件。在一个实施例中，封装组件包括嵌入到直接耦合到附接到子封装的另一管芯的子封装中的管芯。在一些实施例中，子包还可以包含电源管理装置。在一些实施例中，嵌入在子封装和/或功率管理器件中的管芯可以与耦合到子封装的管芯定义的区域重叠或位于其中，使得它们位于耦合到子封装的管芯和衬底之间子包。可以描述和/或要求保护其他实施例。

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