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31. 发明申请

US20100297837A1 Implantation using a hardmask 有权
标题翻译：使用硬掩模进行植入
公开(公告)号：US20100297837A1
公开(公告)日：2010-11-25
申请号：US12469710
申请日：2009-05-21
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/8234 , H01L21/266
CPC分类号： H01L21/266 , H01L21/823892
摘要： A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be a semiconductor substrate. The method further includes performing a first ion implantation, during which, outside the first opening the hardmask is essentially preventing ions from reaching the substrate. The method further involves the application of a photoresist in such a manner that the photoresist is covering the hardmask, and it is also filling up the first opening. This is followed by using the photoresist to pattern the hardmask, whereby the hardmask attains a second opening. The method further includes performing a second ion implantation, during which, outside the second opening, the hardmask and the photoresist, which fills the first opening, are essentially preventing ions from reaching the substrate. The two ion implantations may be used to form the two type of CMOS wells.
摘要翻译：公开了一种用于处理CMOS阱的方法，并且使用单个硬掩模执行多个离子注入。该方法包括在衬底上形成和图案化硬掩模，由此硬掩模获得第一开口。衬底可以是半导体衬底。该方法还包括执行第一离子注入，其间在第一开口外部，硬掩模基本上防止离子到达衬底。该方法还涉及以光致抗蚀剂覆盖硬掩模的方式施加光致抗蚀剂，并且其还填充第一开口。然后使用光致抗蚀剂来模拟硬掩模，由此硬掩模获得第二开口。该方法还包括执行第二离子注入，其间在第二开口外部，填充第一开口的硬掩模和光致抗蚀剂基本上防止离子到达衬底。两个离子注入可用于形成两种类型的CMOS阱。

32. 发明授权

US08901619B2 Asymmetric FinFET devices 有权
标题翻译：非对称FinFET器件
公开(公告)号：US08901619B2
公开(公告)日：2014-12-02
申请号：US13470393
申请日：2012-05-14
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L27/148 , H01L21/263 , H01L29/78 , H01L29/66 , H01L21/265 , H01L29/51
CPC分类号： H01L29/66795 , H01L21/2633 , H01L21/26506 , H01L21/26586 , H01L29/517 , H01L29/785 , H01L29/7855 , H01L29/7856
摘要： Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.
摘要翻译：公开了非对称FET器件，以及在翅片结构上制造这种非对称器件的方法。该制造方法包括在散热片上布置高k电介质层，随后是阈值修饰层，以倾斜角执行离子轰击，该倾斜角度在翅片的侧面之一上除去阈值修饰层。完成的FET器件将是不对称的，因为阈值修饰层仅存在于翅片一侧的两个器件之一中。在替代实施例中，引入另外的不对称性，再次使用倾斜离子注入，导致用于翅片每侧上的两个FinFET器件的不同的栅极 - 导体材料。

33. 发明授权

US08525235B2 Multiplying pattern density by single sidewall imaging transfer 有权
标题翻译：通过单侧壁成像转移乘以图案密度
公开(公告)号：US08525235B2
公开(公告)日：2013-09-03
申请号：US13552205
申请日：2012-07-18
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/76 , H01L23/58
CPC分类号： H01L29/66795 , H01L21/0337 , H01L21/3086 , H01L29/66818
摘要： A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to form at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed.
摘要翻译：一种用于制造集成电路的方法包括在待图案化的层上图案化心轴。将掺杂剂注入到心轴的暴露的侧壁中以形成至少两个具有至少一个与掺杂层相邻的未掺杂区域的掺杂层。选择性地蚀刻去除掺杂层以从未掺杂的区域形成柱。使用柱作为蚀刻掩模蚀刻待图案化的层以形成用于集成电路器件的特征。还公开了一种半导体器件。

34. 发明授权

US08324058B2 Contacts for FET devices 有权
标题翻译： FET器件的触点
公开(公告)号：US08324058B2
公开(公告)日：2012-12-04
申请号：US12941042
申请日：2010-11-06
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
IPC分类号： H01L21/336 , H01L21/76 , H01L21/4763 , H01L21/44
CPC分类号： H01L29/41733 , H01L21/28518 , H01L23/485 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.
摘要翻译：公开了一种接触FET器件的方法。该方法包括垂直凹陷器件隔离，其暴露源极和漏极两侧的侧壁表面。接下来，进行硅化，得到覆盖源极和漏极的顶表面和侧壁表面的硅化物层。接下来，以这样的方式施加金属触点，使得它们在其顶部和侧壁表面上接合硅化物层。还公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。硅化物层覆盖源极和漏极的顶表面和侧壁表面。与设备的金属接触件在其顶表面和其侧壁表面上接合硅化物。

35. 发明授权

US08318570B2 Enhancing MOSFET performance by optimizing stress properties 有权
标题翻译：通过优化应力性能来提高MOSFET性能
公开(公告)号：US08318570B2
公开(公告)日：2012-11-27
申请号：US12628724
申请日：2009-12-01
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/00
CPC分类号： H01L29/7843 , H01L21/26586 , H01L21/31155 , H01L21/823807 , H01L21/823864 , H01L29/6659 , H01L29/7833
摘要： A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas fainted in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.
摘要翻译：用于提高晶体管性能的器件和方法包括形成在其间具有间隔的衬底上的栅极结构。栅极结构形成为与衬底中暗淡的有源区域的操作关系。在栅极结构上形成应力衬垫。角度离子注入施加到应力衬垫上，使得离子被引导到应力衬垫的垂直表面，其中应力衬垫与有源区域接触的部分由于由高度和间隔提供的阴影效应而被屏蔽离子相邻结构之间。

36. 发明授权

US08053809B2 Device including high-K metal gate finfet and resistive structure and method of forming thereof 有权
标题翻译：包括高K金属栅极和电阻结构的器件及其形成方法
公开(公告)号：US08053809B2
公开(公告)日：2011-11-08
申请号：US12471872
申请日：2009-05-26
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/66
CPC分类号： H01L27/1211 , H01L27/0629 , H01L27/1203 , H01L29/517
摘要： A device is provided that in one embodiment includes a substrate having a first region and a second region, in which a semiconductor device is present on a dielectric layer in the first region of the substrate and a resistive structure is present on the dielectric layer in the second region of the substrate. The semiconductor device may include a semiconductor body and a gate structure, in which the gate structure includes a gate dielectric material present on the semiconducting body and a metal gate material present on the gate dielectric material. The resistive structure may include semiconductor material having a lower surface is in direct contact with the dielectric layer in the second region of the substrate. The resistive structure may be a semiconductor containing fuse or a polysilicon resistor. A method of forming the aforementioned device is also provided.
摘要翻译：提供了一种器件，其在一个实施例中包括具有第一区域和第二区域的衬底，其中半导体器件存在于衬底的第一区域中的电介质层上，电阻结构存在于介电层中第二区域。半导体器件可以包括半导体本体和栅极结构，其中栅极结构包括存在于半导体本体上的栅极电介质材料和存在于栅极电介质材料上的金属栅极材料。电阻结构可以包括具有下表面的半导体材料与衬底的第二区域中的电介质层直接接触。电阻结构可以是包含半导体的熔丝或多晶硅电阻器。还提供了一种形成上述装置的方法。

37. 发明授权

US08021949B2 Method and structure for forming finFETs with multiple doping regions on a same chip 有权
标题翻译：在同一芯片上形成具有多个掺杂区域的finFET的方法和结构
公开(公告)号：US08021949B2
公开(公告)日：2011-09-20
申请号：US12628663
申请日：2009-12-01
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/331
CPC分类号： H01L29/66803 , H01L21/26586
摘要： A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantation is applied to one side of the first semiconductor structure to dope a respective fin on the one side. The first semiconductor structure is selectively removed to expose the fins. Fin field effect transistors are formed using the fins.
摘要翻译：一种用于集成电路的特征的制造方法包括在半导体器件的表面上形成第一半导体结构，并且在第一半导体结构的相对侧上外延生长半导体材料，以形成鳍片。第一成角度的离子注入被施加到第一半导体结构的一侧以在一侧上掺杂相应的翅片。选择性地去除第一半导体结构以暴露鳍片。鳍状场效应晶体管使用鳍形成。

38. 发明申请

US20110127588A1 ENHANCING MOSFET PERFORMANCE BY OPTIMIZING STRESS PROPERTIES 有权
标题翻译：通过优化应力特性提高MOSFET的性能
公开(公告)号：US20110127588A1
公开(公告)日：2011-06-02
申请号：US12628724
申请日：2009-12-01
申请人： KANGGUO CHENG , Bruce B. Doris , Ying Zhang
发明人： KANGGUO CHENG , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7843 , H01L21/26586 , H01L21/31155 , H01L21/823807 , H01L21/823864 , H01L29/6659 , H01L29/7833
摘要： A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas fainted in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.
摘要翻译：用于提高晶体管性能的器件和方法包括形成在其间具有间隔的衬底上的栅极结构。栅极结构形成为与衬底中暗淡的有源区域的操作关系。在栅极结构上形成应力衬垫。角度离子注入施加到应力衬垫上，使得离子被引导到应力衬垫的垂直表面，其中应力衬垫与有源区域接触的部分由于由高度和间隔提供的阴影效应而被屏蔽离子相邻结构之间。

39. 发明申请

US20110108961A1 DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS 有权
标题翻译：具有形成具有多个宽度的FINS的装置和方法
公开(公告)号：US20110108961A1
公开(公告)日：2011-05-12
申请号：US12614986
申请日：2009-11-09
申请人： KANGGUO CHENG , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： KANGGUO CHENG , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/06 , H01L21/302
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.
摘要翻译：一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

40. 发明授权

US07919379B2 Dielectric spacer removal 有权
标题翻译：介质垫片去除
公开(公告)号：US07919379B2
公开(公告)日：2011-04-05
申请号：US11852906
申请日：2007-09-10
申请人： Eduard A. Cartier , Rashmi Jha , Sivananda Kanakasabapathy , Xi Li , Renee T. Mo , Vijay Narayanan , Vamsi Paruchuri , Mark T. Robson , Kathryn T. Schonenberg , Michelle L. Steen , Richard Wise , Ying Zhang
发明人： Eduard A. Cartier , Rashmi Jha , Sivananda Kanakasabapathy , Xi Li , Renee T. Mo , Vijay Narayanan , Vamsi Paruchuri , Mark T. Robson , Kathryn T. Schonenberg , Michelle L. Steen , Richard Wise , Ying Zhang
IPC分类号： H01L21/00 , H01L21/336
CPC分类号： H01L21/31116 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.
摘要翻译：本发明涉及半导体器件，更具体地说，涉及一种基本上不去除半导体衬底去除对半导体衬底的表面有选择性的介电隔离层的工艺和结构。本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。该方法包括在半导体衬底上形成场效应晶体管，所述FET包括电介质间隔物和所述栅极结构，所述电介质隔离物邻近所述栅极结构的侧壁并位于所述半导体衬底中的源极/漏极区域上; 在FET上沉积第一氮化物层; 并且基本上不去除半导体衬底，去除对半导体衬底的选择性的氮化物层和电介质衬垫。

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