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    • 33. 发明授权
    • Substrate-on-insulator semiconductor device with noise decoupling
    • 具有噪声去耦的绝缘体上半导体器件衬底
    • US06285071B1
    • 2001-09-04
    • US09466728
    • 1999-12-17
    • Didier Belot
    • Didier Belot
    • H01L2900
    • H01L24/49H01L23/66H01L24/48H01L2224/05553H01L2224/48247H01L2224/48257H01L2224/49171H01L2924/00014H01L2924/01006H01L2924/01014H01L2924/01015H01L2924/01027H01L2924/01051H01L2924/01058H01L2924/01074H01L2924/14H01L2924/19041H01L2924/30105H01L2924/30107H01L2924/3011H01L2924/00H01L2224/45099
    • A semiconductor device of the type having an integrated circuit with connection terminals connected to metal pads by connecting wires is provided. The integrated circuit includes a substrate-on-insulator type semiconductor substrate having a lower portion on top of which there is an upper insulating layer. A first semiconductor block and a second semiconductor block are produced in the upper insulating layer, and decoupling means are arranged in the upper insulating layer between the first and second semiconductor blocks. The first semiconductor block defines a first capacitor with the lower portion of the substrate, the second semiconductor block defines a second capacitor with the lower portion of the substrate, and the decoupling means includes at least one semiconductor well that defines a decoupling capacitor with the lower portion of the substrate. The capacitance of the decoupling capacitor is higher than the capacitance of each of the first and second capacitors. Also provided is a method of providing noise decoupling in an integrated circuit having a substrate-on-insulator type semiconductor substrate with a lower portion on top of which there is an upper insulating layer.
    • 提供一种具有集成电路的类型的半导体器件,其具有通过连接线连接到金属焊盘的连接端子。 集成电路包括绝缘体上半导体衬底,其上部具有上部绝缘层的下部。 第一半导体块和第二半导体块被制造在上绝缘层中,并且去耦装置被布置在第一和第二半导体块之间的上绝缘层中。 第一半导体块限定具有衬底的下部的第一电容器,第二半导体块限定具有衬底的下部的第二电容器,并且去耦装置包括至少一个半导体阱,该半导体阱限定具有下部电极的去耦电容器 部分基板。 去耦电容器的电容高于第一和第二电容器的电容。 还提供了一种在具有绝缘体上半导体衬底的集成电路中提供噪声去耦的方法,其上部具有上绝缘层。
    • 34. 发明授权
    • Circuit for detecting reception errors in an asynchronous transmission
    • 用于检测异步传输中的接收错误的电路
    • US06195784B1
    • 2001-02-27
    • US09082927
    • 1998-05-21
    • Didier Belot
    • Didier Belot
    • G06F1100
    • H04L7/033
    • The present invention relates to a circuit of reception of bits transmitted on an asynchronous signal, including a circuit for providing a clock reconstructed from the asynchronous signal, this clock being used to sample the asynchronous signal to form a synchronous output signal, and a reception error detection circuit. The reception error detection circuit includes an edge detector providing a detection pulse for each edge of predetermined direction of the asynchronous signal; and an alarm circuit activating an alarm signal when an edge of predetermined direction of the synchronous signal occurs outside a detection pulse.
    • 本发明涉及一种在异步信号上发送的比特的接收电路,包括用于提供从异步信号重建的时钟的电路,该时钟用于采样异步信号以形成同步输出信号,以及接收错误 检测电路。 接收错误检测电路包括边缘检测器,为异步信号的预定方向的每个边缘提供检测脉冲; 以及当同步信号的预定方向的边缘出现在检测脉冲之外时启动报警信号的报警电路。
    • 35. 发明授权
    • Phase-shifting device for antenna array
    • 天线阵列相移装置
    • US08982994B2
    • 2015-03-17
    • US13328412
    • 2011-12-16
    • Mathieu EgotJonathan MullerAndreia CathelinDidier Belot
    • Mathieu EgotJonathan MullerAndreia CathelinDidier Belot
    • H04L25/49H01Q3/26
    • H01Q3/26
    • Device comprising processing means (MT), transmission channels (VE1, . . . VEn), an antenna array for transmitting signals comprising a number of antennas (A11 . . . A1n) respectively associated with the transmission channels, a number of digital-analog converters (DAC) and a number of phase-shifting means (MD1, . . . MDn) respectively associated with the antennas, said phase-shifting means (MD1, . . . MDn) being placed between the processing means (MT) and the digital-analog converters (DAC) and including digital all-pass filters of FIR type (PT), the processing means comprising control means (MC) configured to adjust the coefficients and/or the order of the all-pass filters of FIR type.
    • 包括处理装置(MT),传输信道(VE1,...,VEn)的装置,用于发送包括分别与传输信道相关联的多个天线(A11 ... A1n)的信号的天线阵列,数字模拟 分别与天线相关联的多个转换器(DAC)和多个移相装置(MD1,...,MDn),所述移相装置(MD1,...,MDn)被放置在处理装置(MT)和 数模转换器(DAC)并且包括FIR类型(PT)的数字全通滤波器,所述处理装置包括被配置为调整FIR类型的全通滤波器的系数和/或顺序的控制装置(MC)。