专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US06259142B1 Multiple split gate semiconductor device and fabrication method 失效
标题翻译：多分裂栅极半导体器件及其制造方法
公开(公告)号：US06259142B1
公开(公告)日：2001-07-10
申请号：US09056837
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L2976
CPC分类号： H01L29/66484 , H01L29/7831
摘要： A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another by means of a gate insulating layer that is formed adjacent the side-walls of each firs gate electrode. Source and drain regions are formed adjacent the ends of the multiple split gate to define a channel region.
摘要翻译：具有多个分割栅极的半导体集成电路使用第一多晶硅层和第二多晶硅层形成，以在有源区内形成交替的第一和第二栅电极。交替的栅电极通过与每个第一栅电极的侧壁相邻形成的栅极绝缘层彼此电隔离。源极和漏极区域形成在多分裂栅极的端部附近以限定沟道区域。

32. 发明授权

US06204148B1 Method of making a semiconductor device having a grown polysilicon layer 有权
标题翻译：制造具有生长的多晶硅层的半导体器件的方法
公开(公告)号：US06204148B1
公开(公告)日：2001-03-20
申请号：US09329843
申请日：1999-06-11
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L2176
CPC分类号： H01L29/66583
摘要： A partially formed semiconductor device includes a substrate, a first layer, a layer of polysilicon, and a grown layer of polysilicon. The first layer is positioned above at least a portion of the substrate. The layer of polysilicon is positioned above at least a portion of the first layer and has a first opening formed therein. The first opening has a first width that is defined by a plurality of sidewalls. The grown layer of polysilicon is positioned adjacent at least the plurality of sidewalls and the grown layer of polysilicon defines a second opening. The second opening has a second width with the second width being less than the first width. A method for partially forming a semiconductor device includes forming a process layer above at least a portion of a substrate. A layer of polysilicon is formed above at least a portion of the process layer. An opening is formed in the layer of polysilicon, and the opening has a first width that is defined by a plurality of sidewalls. The first width of the opening is reduced to a second width by growing a layer of polysilicon adjacent at least a portion of the sidewalls of the opening.
摘要翻译：部分形成的半导体器件包括衬底，第一层，多晶硅层和生长的多晶硅层。第一层位于衬底的至少一部分上方。多晶硅层位于第一层的至少一部分的上方，并且其中形成有第一开口。第一开口具有由多个侧壁限定的第一宽度。多晶硅生长层位于至少多个侧壁附近，并且生长的多晶硅层限定第二开口。第二开口具有第二宽度，第二宽度小于第一宽度。部分形成半导体器件的方法包括在衬底的至少一部分上方形成工艺层。在工艺层的至少一部分上方形成多晶硅层。在多晶硅层中形成开口，并且开口具有由多个侧壁限定的第一宽度。通过在开口的侧壁的至少一部分附近生长一层多晶硅，将开口的第一宽度减小到第二宽度。

33. 发明授权

US06201278B1 Trench transistor with insulative spacers 失效
标题翻译：带绝缘垫片的沟槽晶体管
公开(公告)号：US06201278B1
公开(公告)日：2001-03-13
申请号：US09028896
申请日：1998-02-24
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L31062
CPC分类号： H01L29/7834 , H01L29/66621
摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.
摘要翻译：公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与栅电极。有利地，沟道长度明显小于沟槽长度。

34. 发明授权

US6100146A Method of forming trench transistor with insulative spacers 失效
标题翻译：用绝缘间隔物形成沟槽晶体管的方法
公开(公告)号：US6100146A
公开(公告)日：2000-08-08
申请号：US739595
申请日：1996-10-30
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7834 , H01L29/66621
摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.
摘要翻译：公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与栅电极。有利地，沟道长度明显小于沟槽长度。

35. 发明授权

US06080629A Ion implantation into a gate electrode layer using an implant profile displacement layer 失效
标题翻译：使用植入物轮廓位移层将离子注入到栅极电极层中
公开(公告)号：US06080629A
公开(公告)日：2000-06-27
申请号：US837579
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/28035
摘要： A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into underlying structures.
摘要翻译：将掺杂剂注入到薄栅电极层中的方法包括在栅电极层上形成位移层以形成组合位移/栅极电极层，并将掺杂剂注入到组合层中。注入的掺杂剂分布基本上完全位于栅极电极层内，或者基本上部分地位于栅极电极层内部分地位于位移层内。如果位移层最终被去除，则注入的掺杂剂的至少一部分保留在栅电极层内。栅极电极层可以在图案化之前或之后被注入，并蚀刻栅电极层以限定栅电极。此外，可以使用两种不同的选择性植入来限定不同掺杂剂浓度的分开的区域，例如P型多晶硅和N型多晶硅区域。每个区域可以利用单独的位移层厚度，这允许不同原子质量的掺杂剂使用类似的注入能量。可以使用较高的注入能量来掺杂比正常范围统计要求更薄的栅极电极层，而不会使植入物渗入下面的结构。

36. 发明授权

US6048785A Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching 失效
标题翻译：半导体制造方法，其使用片段拼接来组合由标线片图像定义的多个场
公开(公告)号：US6048785A
公开(公告)日：2000-04-11
申请号：US876628
申请日：1997-06-16
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76895 , Y10S438/946 , Y10S438/949
摘要： Each region of multiple regions on a semiconductor substrate is imaged in an exposure field defined by a reticle. The regions are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The regions are interconnected by imaging using a stitching reticle having an exposure field overlapping a plurality of the regions. The combination of reticle-imaged fields effectively increases the size of a field formed using a step and repeat technique while achieving high imaging resolution within the combined regions. Similarly, a plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are interconnected using a stitch mask and etch operation that combines the regions.
摘要翻译：在半导体衬底上的多个区域的每个区域以由掩模版定义的曝光区域成像。这些区域通过诸如场氧化物或沟槽隔离的隔离在半导体衬底内分离和电隔离。这些区域通过使用具有与多个区域重叠的曝光场的拼接掩模版进行成像来互连。掩模版成像场的组合有效地增加了使用步骤和重复技术形成的场的大小，同时在组合区域内实现高成像分辨率。类似地，使用多个集成芯片组中的每一个的单独掩模版成像，在单个半导体晶片上构造包括微处理器，存储器和支持芯片的多个集成芯片组。使用组合这些区域的针迹掩模和蚀刻操作来使不同的电路互连。

37. 发明授权

US5937299A Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls 失效
标题翻译：用于形成具有硅化物源极/漏极接触的IGFET的方法，其紧邻具有倾斜侧壁的栅极
公开(公告)号：US5937299A
公开(公告)日：1999-08-10
申请号：US837522
申请日：1997-04-21
申请人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
发明人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/08 , H01L29/417 , H01L29/423
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/0847 , H01L29/41775 , H01L29/42376 , H01L29/66628 , H01L29/665
摘要： An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide. In this manner, a highly miniaturized IGFET can be provided with densely-packed gate, source and drain contacts without the need for sidewall spacers adjacent to the gate.
摘要翻译：公开了具有源极和漏极触点的IGFET，其紧邻具有倾斜侧壁的栅极。制造IGFET的方法包括在半导体衬底上形成栅极，其中栅极包括顶表面，底表面和相对的侧壁，并且顶表面具有比底表面大得多的长度，形成源极和漏极延伸到衬底中，在栅极，源极和漏极上沉积接触材料，以及在栅极上形成栅极接触，源极上的源极接触和漏极上的漏极接触。由于栅极侧壁的逆向斜坡，栅极与源极和漏极接触分离，并且由于接触材料中缺少台阶覆盖，栅极接触与源极和漏极接触分离。优选地，接触材料是难熔金属，并且通过将难熔金属转化为硅化物形成触点。以这种方式，高度小型化的IGFET可以设置有密集封装的栅极，源极和漏极接触，而不需要邻近栅极的侧壁间隔。

38. 发明授权

US5918126A Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size 失效
标题翻译：使用偏置差分制造具有不同器件密度的器件的集成电路的制造方法，以形成具有均匀尺寸的器件
公开(公告)号：US5918126A
公开(公告)日：1999-06-29
申请号：US805796
申请日：1997-02-25
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/8234
CPC分类号： H01L21/32139 , H01L21/28123 , H01L21/823456
摘要： It has been discovered that different pattern densities that occur in conventional lithography produce a different final etch polysilicon gate width in high density (dense) regions of polysilicon gates as compared to low density (isolated) polysilicon gate regions. The final etch polysilicon gate width for a dense region is smaller by a predictable distance relative to the final etch polysilicon gate width for an isolated region. For example, a typical dense region has a final etch polysilicon gate width that is approximately 0.05 .mu.m smaller relative to the final etch polysilicon gate width of isolated regions having a channel length of 0.35 .mu.m. A biasing technique is employed for a polysilicon masking reticle in which the reticle is biased differently in regions of isolated polysilicon gates in comparison to regions of dense polysilicon gates. More specifically, in one embodiment the polysilicon masking reticle is increased in size in regions of high density polysilicon gates in comparison to regions of isolated polysilicon gates. In another embodiment, the reticle in regions of isolated polysilicon gates is sized normally but increased in size in regions of high density polysilicon gates. Following photomasking and etching, substantially identical polysilicon lengths are achieved in the isolated and dense gate regions.
摘要翻译：已经发现，与低密度（隔离）多晶硅栅极区域相比，在常规光刻中发生的不同图案密度在多晶硅栅极的高密度（密集）区域中产生不同的最终蚀刻多晶硅栅极宽度。用于密集区域的最终蚀刻多晶硅栅极宽度相对于隔离区域的最终蚀刻多晶硅栅极宽度可预测的距离较小。例如，典型的密集区域具有最终蚀刻多晶硅栅极宽度，相对于沟道长度为0.35μm的隔离区域的最终蚀刻多晶硅栅极宽度大约为0.05μm。对于多晶硅掩模掩模版采用偏置技术，其中与致密多晶硅栅极的区域相比，掩模版在隔离多晶硅栅极的区域中被不同地偏置。更具体地，在一个实施例中，与隔离多晶硅栅极的区域相比，多晶硅掩模掩模版的尺寸在高密度多晶硅栅极的区域中增加。在另一个实施例中，隔离多晶硅栅极的区域中的掩模版尺寸正常，但在高密度多晶硅栅极的区域中的尺寸增大。在光掩模和蚀刻之后，在隔离和密集的栅极区域中实现了基本相同的多晶硅长度。

39. 发明授权

US5874343A CMOS integrated circuit and method for forming source/drain areas prior to forming lightly doped drains to optimize the thermal diffusivity thereof 失效
标题翻译： CMOS集成电路和在形成轻掺杂漏极之前形成源极/漏极区域以优化其热扩散率的方法
公开(公告)号：US5874343A
公开(公告)日：1999-02-23
申请号：US760464
申请日：1996-12-06
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L21/70
CPC分类号： H01L21/823814
摘要： A transistor and a transistor fabrication method in which the heavy source/drain implants which require high-temperature thermal anneals are performed before the LDD implants which require lower temperature thermal anneals. In addition, the n-type arsenic source/drain implant which requires the highest temperature anneal is performed prior to the p-type boron implant which requires a lower temperature thermal anneal. In a conventional LDD, the LDD implants are performed first, prior to the source/drain implants. The LDD implants, especially the p-type boron implants, are annealed at a relatively low temperature. The source/drain implants require a higher thermal anneal temperature since they need to diffuse a longer distance. The n-type arsenic source/drain implants require an especially high temperature since arsenic is relatively large ion with a low diffusivity. During the high temperature thermal anneal, the LDD implants that are already present will migrate significantly. Lateral migration towards the channel will shorten the channel length and cause short-channel effects, and vertical migration into the substrate will cause an increase of the parasitic capacitance. The current invention reverses the formation process to avoid such problems. The n-type arsenic source/drain implant is performed first, and the p-type LDD implant is performed last.
摘要翻译：晶体管和晶体管制造方法，其中需要高温热退火的重源/漏植入物在需要较低温度热退火的LDD植入物之前进行。此外，需要最高温度退火的n型砷源/漏极注入在需要较低温度热退火的p型硼注入之前进行。在传统的LDD中，LDD植入物首先在源/漏植入物之前进行。 LDD植入物，特别是p型硼植入物在相对较低的温度下进行退火。源/漏植入物需要更高的热退火温度，因为它们需要扩散更长的距离。 n型砷源/漏植入物需要特别高的温度，因为砷具有较低的扩散系数的相对较大的离子。在高温热退火期间，已经存在的LDD植入物将显着迁移。向通道的侧向迁移将缩短沟道长度并引起短沟道效应，并且垂直迁移到衬底将导致寄生电容的增加。本发明逆转了形成过程以避免这种问题。首先进行n型砷源/漏极注入，最后执行p型LDD植入。

40. 发明授权

US5854121A Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure 失效
标题翻译：半导体制造采用掺入沟槽隔离结构边缘的势垒原子
公开(公告)号：US5854121A
公开(公告)日：1998-12-29
申请号：US923184
申请日：1997-09-04
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/316 , H01L21/762 , H01L21/302
CPC分类号： H01L21/02233 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/31612 , H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 .ANG.. The semiconductor topography is then exposed to a barrier-entrained gas and heated so that barrier atoms become incorporated in regions of the active areas in close proximity to the trench isolation structure. The masking layer may prevent the barrier atoms from being incorporated into any other regions of the substrate.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在半导体衬底上形成电介质掩模层。然后通过掩模层形成开口。在开口内的掩模层的侧壁上形成一对电介质隔离物。然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。然后在沟槽的壁和基底上热生长第一介电层。将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。间隔物的部分也被去除，使得间隔物的厚度在约0至200安培之间。然后将半导体形貌暴露于阻挡夹带气体并加热，使得势垒原子并入到紧邻沟槽隔离结构的有源区域的区域中。掩模层可以防止阻挡原子被结合到衬底的任何其它区域中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式