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31. 发明授权

US07253124B2 Process for defect reduction in electrochemical plating 有权
标题翻译：电化学电镀中缺陷减少的工艺
公开(公告)号：US07253124B2
公开(公告)日：2007-08-07
申请号：US09971210
申请日：2001-10-04
申请人： Jiong-Ping Lu , Patricia B. Smith
发明人： Jiong-Ping Lu , Patricia B. Smith
IPC分类号： H01L21/26
CPC分类号： H01L21/76864 , H01L21/02068 , H01L21/321 , H01L21/76838 , H01L21/76843 , H01L21/76873
摘要： A pre-ECD surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with an H2 plasma to remove surface contamination (122), reduce any CuOx (123), and improve wettability. The ECD copper film (124) is then formed over the seed layer (112).
摘要翻译：前ECD表面处理。在形成阻挡材料（110）和种子层（112）之后，种子层（112）的表面用H 2 H 2等离子体处理以除去表面污染物（122），减少任何CuO （123），并提高润湿性。然后在种子层（112）上形成ECD铜膜（124）。

32. 发明申请

US20070063294A1 Semiconductor Device Having a Fully Silicided Gate Electrode and Method of Manufacture Therefor 审中-公开
标题翻译：具有全硅酸盐栅电极的半导体器件及其制造方法
公开(公告)号：US20070063294A1
公开(公告)日：2007-03-22
申请号：US11556834
申请日：2006-11-06
申请人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
发明人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00 , H01L27/108 , H01L31/119
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823835 , H01L21/823864 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).
摘要翻译：本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。除了其它可能的元件之外，半导体器件（100）包括位于衬底（110）上方的硅化栅电极（150），硅化栅电极（150）具有位于其侧壁上的栅极侧壁间隔物（160）。半导体器件（100）还包括位于靠近硅化物栅电极（150）的衬底（110）中的源/漏区（170）和位于源/漏区（170）中的硅化源/漏区（180）并且至少部分地在栅极侧壁间隔件（160）下方。

33. 发明授权

US07183187B2 Integration scheme for using silicided dual work function metal gates 有权
标题翻译：使用硅化双功能金属门的集成方案
公开(公告)号：US07183187B2
公开(公告)日：2007-02-27
申请号：US10851750
申请日：2004-05-20
申请人： Jiong-Ping Lu , Gregory Shinn , Ping Jiang
发明人： Jiong-Ping Lu , Gregory Shinn , Ping Jiang
IPC分类号： H01L21/3205
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L27/0811 , H01L28/60
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, includes forming a polysilicon gate electrode (250) over a substrate (210) and forming source/drain regions (610) in the substrate (210) proximate the polysilicon gate electrode (250). The method further includes forming a protective layer (710) over the source/drain regions (610) and the polysilicon gate electrode (250), then removing the protective layer (710) from over a top surface of the polysilicon gate electrode (250) while leaving the protective layer (710) over the source/drain regions (250). After the protective layer (710) has been removed from over the top surface of the polysilicon gate electrode (250), the polysilicon gate electrode (250) is silicided to form a silicided gate electrode (1310). The protective layer (710) is also removed from over the source/drain regions (610) and source/drain contact regions (1610) are formed.
摘要翻译：本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。除了其他可能的步骤之外，制造半导体器件的方法包括在衬底（210）上形成多晶硅栅电极（250），并在靠近多晶硅栅电极（250）的衬底（210）中形成源/漏区（610））。该方法还包括在源极/漏极区域（610）和多晶硅栅电极（250）之上形成保护层（710），然后从多晶硅栅电极（250）的顶表面上方移除保护层（710）同时将保护层（710）留在源/漏区（250）上。在保护层（710）已从多晶硅栅电极（250）的顶表面上方移除之后，多晶硅栅电极（250）被硅化以形成硅化栅电极（1310）。保护层（710）也从源极/漏极区域（610）上去除并形成源极/漏极接触区域（1610）。

34. 发明授权

US07101788B2 Semiconductor devices and methods of manufacturing such semiconductor devices 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07101788B2
公开(公告)日：2006-09-05
申请号：US10342013
申请日：2003-01-14
申请人： Patricia Beauregard Smith , Jiong-Ping Lu
发明人： Patricia Beauregard Smith , Jiong-Ping Lu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76802 , H01L21/76826
摘要： A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (102), forming a dielectric layer (104) over the semiconductor substrate (102), and etching a trench structure (106) or a via structure (106) in the dielectric layer (104) to expose a portion of a surface of the semiconductor substrate (102). The method also includes the steps of treating a surface (104a) of the dielectric layer (104) with an adhesion solution, such as a reactive plasma including hydrogen, and forming a diffusion barrier layer (110) over the dielectric layer (104). Moreover, the adhesion solution chemically interacts with the surface (104a) of the dielectric layer (104) and enhances or increases adhesion between dielectric layer (104) and diffusion barrier layer (110).
摘要翻译：一种制造半导体器件的方法包括以下步骤：提供半导体衬底（102），在半导体衬底（102）上形成电介质层（104），以及蚀刻沟槽结构（106）或通孔结构（106）所述电介质层（104）暴露所述半导体衬底（102）的表面的一部分。该方法还包括以下步骤：用诸如包含氢的反应性等离子体等粘合溶液处理电介质层（104）的表面（104a），并在介电层（104）上形成扩散阻挡层（110）。此外，粘附溶液与电介质层（104）的表面（104a）化学相互作用并且增强或增加介电层（104）和扩散阻挡层（110）之间的粘附。

35. 发明授权

US07098094B2 NiSi metal gate stacks using a boron-trap 有权
标题翻译： NiSi金属栅堆叠使用硼陷阱
公开(公告)号：US07098094B2
公开(公告)日：2006-08-29
申请号：US10734768
申请日：2003-12-12
申请人： Jiong-Ping Lu
发明人： Jiong-Ping Lu
IPC分类号： H01L21/8238 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/28097 , H01L21/823835
摘要： A capping layer (118) is used during an anneal to form fully silicided NiSi gate electrodes (120). The capping layer (118) comprises a material with an affinity for boron, such as TiN. The capping layer (118) serves as a boron trap that reduces the interface boron concentration for PMOS transistors without reducing the interface arsenic concentration for NMOS transistors.
摘要翻译：在退火期间使用覆盖层（118）以形成完全硅化的NiSi栅电极（120）。覆盖层（118）包括对硼具有亲和性的材料，例如TiN。覆盖层（118）用作硼阱，其降低PMOS晶体管的界面硼浓度，而不降低NMOS晶体管的界面砷浓度。

36. 发明申请

US20050215055A1 Semiconductor device having a fully silicided gate electrode and method of manufacture therefor 有权
标题翻译：具有全硅化物栅电极的半导体器件及其制造方法
公开(公告)号：US20050215055A1
公开(公告)日：2005-09-29
申请号：US10808168
申请日：2004-03-24
申请人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
发明人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823835 , H01L21/823864 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).
摘要翻译：本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。除了其它可能的元件之外，半导体器件（100）包括位于衬底（110）上方的硅化栅电极（150），硅化栅电极（150）具有位于其侧壁上的栅极侧壁间隔物（160）。半导体器件（100）还包括位于靠近硅化物栅电极（150）的衬底（110）中的源/漏区（170）和位于源/漏区（170）中的硅化源/漏区（180）并且至少部分地在栅极侧壁间隔件（160）下方。

37. 发明授权

US06641867B1 Methods for chemical vapor deposition of tungsten on silicon or dielectric 有权
标题翻译：在硅或电介质上钨化学气相沉积的方法
公开(公告)号：US06641867B1
公开(公告)日：2003-11-04
申请号：US09276043
申请日：1999-03-25
申请人： Wei-Yung Hsu , Jiong-Ping Lu , August J. Fischer , Ming-Jang Hwang
发明人： Wei-Yung Hsu , Jiong-Ping Lu , August J. Fischer , Ming-Jang Hwang
IPC分类号： B05D512
CPC分类号： H01L21/76843 , C23C16/08 , H01L21/28061 , H01L21/28556 , H01L21/32051 , H01L21/76856 , H01L21/76876 , H01L21/76877
摘要： In situ nitridation of a thin layer of either silicon or tungsten provides an adhesive layer for bulk deposition of tungsten. Alternatively, a thin layer of silicon can be deposited directly on a dielectric, then reacted with WF6 to replace the silicon with tungsten, which provides a nucleation layer for bulk tungsten deposition.
摘要翻译：硅或钨的薄层的原位氮化提供了用于钨的体积沉积的粘合剂层。或者，可以将薄的硅层沉积在电介质上，然后与WF6反应以用钨代替硅，其提供用于体钨沉积的成核层。

38. 发明授权

US06559050B1 Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices 有权
标题翻译：制造亚微米级CMOS器件的高热稳定接触形成工艺
公开(公告)号：US06559050B1
公开(公告)日：2003-05-06
申请号：US09691907
申请日：2000-10-19
申请人： William R. McKee , Jiong-Ping Lu , Ming-Jang Hwang , Dirk N. Anderson , Wei Lee
发明人： William R. McKee , Jiong-Ping Lu , Ming-Jang Hwang , Dirk N. Anderson , Wei Lee
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76855 , H01L21/76856 , H01L21/76867
摘要： A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSiYNZ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i.e., exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via. According to another embodiment, a silicon surface layer is applied to the exposed surface of the dielectric layer and to the exposed surface of the substrate prior to formation of the nitrided surface layer. A layer of tungsten, tungsten/tungsten nitride, or tungsten nitride is formed to fill the via. After annealing, a tungsten conducting plug is formed with a tungsten-silicon-nitride interface region with the substrate.
摘要翻译：与集成电路一起使用的导电插头/接触结构包括形成在通孔中的钨导电插塞，其中钨硅氮化物（WSiYNZ）区域提供钨导电插塞和衬底（硅）层之间的界面。在形成填充通孔的钨/氮化钨层之前，形成界面区域，在暴露的电介质表面和暴露的衬底表面上（即，通过电介质层中的通孔暴露）提供氮化表面层。该结构退火形成导电插塞和基板之间的钨 - 氮化硅界面的钨导电塞。根据另一个实施例，在形成钨层以填充通孔之前，氮化表面层上形成氮化钨表面层。根据另一实施例，在形成氮化表面层之前，将硅表面层施加到介电层的暴露表面和衬底的暴露表面。形成一层钨，钨/氮化钨或氮化钨以填充通孔。在退火之后，形成具有与基板的钨 - 氮化硅界面区域的钨导电塞。

39. 发明授权

US6120842A TiN+Al films and processes 失效
标题翻译： TiN + Al膜和工艺
公开(公告)号：US6120842A
公开(公告)日：2000-09-19
申请号：US954989
申请日：1997-10-21
申请人： Jiong-Ping Lu , Wei-Yung Hsu , Qi-Zhong Hong
发明人： Jiong-Ping Lu , Wei-Yung Hsu , Qi-Zhong Hong
IPC分类号： H01L21/02 , H01L21/285 , H01L21/302
CPC分类号： H01L28/75 , H01L21/28556 , H01L21/28568 , H01L28/55
摘要： A process for producing conformal and stable TiN+Al films, which provides flexibility in selecting the chemical composition and layering. In this new process, porous TiCN is first deposited, and then Al is incorporated by exposing the porous film to CVD aluminum conditions at low temperatures.
摘要翻译：一种生产保形稳定的TiN + Al薄膜的方法，为选择化学成分和分层提供了灵活性。在该新方法中，首先沉积多孔TiCN，然后通过在低温下将多孔膜暴露于CVD铝条件下而引入Al。

40. 发明授权

US6100188A Stable and low resistance metal/barrier/silicon stack structure and related process for manufacturing 失效
标题翻译：稳定和低电阻金属/屏障/硅堆叠结构及相关制造工艺
公开(公告)号：US6100188A
公开(公告)日：2000-08-08
申请号：US108474
申请日：1998-07-01
申请人： Jiong-Ping Lu , Ming Hwang , Dick N. Anderson , Duane E. Carter , Wei-Yung Hsu
发明人： Jiong-Ping Lu , Ming Hwang , Dick N. Anderson , Duane E. Carter , Wei-Yung Hsu
IPC分类号： H01L21/28 , H01L29/49 , H01L21/44
CPC分类号： H01L29/4941 , H01L21/28061
摘要： A metal-poly stack gate structure and associated method for forming a conductive barrier layer between W and poly in the metal-gate stack gate structure. The process includes the steps of depositing doped silicon on a substrate; forming nitride on the deposited silicon; depositing a metal on the nitride to form a metal/nitride/deposited silicon stack; and thermally treating the stack to transform the nitride into a conductive barrier layer between the metal and the deposited silicon. The thermal treatment transforms the nitride layer (SiN.sub.x or SiN.sub.x O.sub.y) into a conductive barrier (WSi.sub.x N.sub.y or WSi.sub.x N.sub.y O.sub.z) to form a W/barrier/poly stack gate structure. The barrier layer blocks reaction between W and Si, enhances sheet resistance, enhances adhesion between the W and the poly, and is stable at high temperatures.
摘要翻译：一种用于在金属 - 栅极堆叠栅极结构中在W和多晶之间形成导电阻挡层的金属 - 多晶堆叠栅极结构和相关联的方法。该方法包括在衬底上沉积掺杂硅的步骤; 在沉积的硅上形成氮化物; 在氮化物上沉积金属以形成金属/氮化物/沉积的硅堆叠; 并且对叠层进行热处理以将氮化物转变成金属和沉积的硅之间的导电阻挡层。热处理将氮化物层（SiN x或SiN x O y）转换成导电屏障（WSixNy或WSixNyOz）以形成W /势垒/多晶堆叠栅极结构。阻挡层阻止W和Si之间的反应，增强了薄层电阻，增强了W和聚硅之间的粘附性，并且在高温下是稳定的。

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