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    • 31. 发明申请
    • Identifying uncorrectable codewords in a Reed-Solomon decoder for errors and erasures
    • 在Reed-Solomon解码器中识别不可纠正的码字以进行错误和擦除
    • US20060174181A1
    • 2006-08-03
    • US10632123
    • 2003-07-30
    • David BanksJonathan JedwabJames Davis
    • David BanksJonathan JedwabJames Davis
    • H03M13/00
    • H03M13/1585H03M13/15H03M13/1515H03M13/157H03M13/1575
    • In a Reed-Solomon decoder handling both errors and erasures, an uncorrectable codeword is identified when any one or more of six conditions (a) to (f) is satisfied: (a) no solution to key equation σ(x)T(x)≡(x)modx2T; (b) degσ(x)≠nerrors; (c) error and erasure locations coincide; (d) deg ω(x)≧nerrors+nerasures; (e) nerasures+2*nerrors>2T; and (f) an error location has a zero correction magnitude. Nerrors and nerasures represent, respectively, a number of errors and erasures, with respect to an error locator polynomial σ(x) and an erasure locator polynomial Λ(x), 2T is the strength of a Reed-Solomon code, ω(x) is an errata evaluator polynomial, and T(x) is a modified syndrome polynomial. A detector circuit 300 comprises a logic unit 350 which tests for the conditions (a) to (g), and an indicator unit 360 which provides a corresponding output.
    • 在处理错误和擦除两者的Reed-Solomon解码器中,当满足六个条件(a)至(f)中的任何一个或多个时,识别出不可校正的码字:(a)对密钥方程sigma(x)T(x )≡(x)modx 2T = nerrors + nerasures; (e)nalsures + 2 * nerrors> 2T; 和(f)误差位置具有零校正量值。 相对于误差定位多项式σ(x)和擦除定位多项式λ(x),误差和误差分别表示许多误差和擦除,2T是Reed-Solomon码的强度,ω(x) 是勘误评估多项式,T(x)是修正的校正子多项式。 检测器电路300包括测试条件(a)至(g)的逻辑单元350以及提供相应输出的指示器单元360。
    • 38. 发明授权
    • Asynchronous transfer mode switch with multicasting ability
    • 具有组播能力的异步传输模式切换
    • US5572522A
    • 1996-11-05
    • US422122
    • 1995-04-13
    • Costas CalamvokisDavid Banks
    • Costas CalamvokisDavid Banks
    • H04Q3/00H04L12/56H04L29/06H04Q3/52H04Q11/04
    • H04L12/5601H04L29/06H04L49/108H04L49/203H04L49/255H04Q11/0478H04L2012/5679H04L2012/5681
    • An ATM switch with multicast capability is provided that internally uses input and output identifiers to identify the cell input and output streams, the relevant input identifier being generated for each cell as it arrives. The apparatus stores both the cell bodies of the cells received by the input means and a respective sequence data set for each input stream. Each sequence data set serves to order the cell bodies received for the corresponding input steam in order of receipt. The sequence data sets are held in a queuing block that includes an input control which upon a new cell body being stored, updates the sequence data set of the input stream to which the cell belongs as identified by the corresponding input identifier. The queuing block also has an output control for maintaining for each output stream a sequence position indicator referencing into the sequence data set of the corresponding input stream to indicate the next cell body to be sent on the output stream concerned. A scheduling block of the apparatus outputs the output identifier of the output stream on which a cell is next to be output. This identifier is used by the output control of the queuing block to look up the corresponding sequence position indicator which it uses, in turn, to reference into the corresponding sequence data set thereby to identify the cell next to be sent on the scheduled output stream. The same queuing arrangement can also be used in systems handling variable-length packets.
    • 提供具有组播能力的ATM交换机,其内部使用输入和输出标识符来识别小区输入和输出流,当每个小区到达时生成相关的输入标识符。 该装置存储由输入装置接收的单元的单元体和针对每个输入流的相应的序列数据集。 每个序列数据集用于按照收到的顺序对相应的输入蒸汽接收的细胞体进行排序。 序列数据集被保存在排队块中,该排队块包括输入控制,该输入控制在被存储的新的单元体被更新为由相应的输入标识符标识的小区所属的输入流的序列数据集。 排队块还具有输出控制,用于为每个输出流维护参考相应输入流的序列数据集的序列位置指示符,以指示要在相关输出流上发送的下一个单元体。 设备的调度块输出下一个要输出单元的输出流的输出标识符。 该标识符由排队块的输出控制使用,以查找其使用的相应序列位置指示符,依次将其引用到对应的序列数据集中,从而识别下一个要在调度的输出流上发送的信元。 在处理可变长度数据包的系统中也可以使用相同的排队方案。
    • 39. 发明授权
    • Cell switch fabric chip
    • 蜂窝交换矩阵芯片
    • US5557610A
    • 1996-09-17
    • US422141
    • 1995-04-14
    • Costas CalamvokisDavid Banks
    • Costas CalamvokisDavid Banks
    • H04Q3/00H04L12/56H04Q3/52H04Q11/04
    • H04L12/5601H04L49/108H04L49/255H04Q11/0478
    • A cell switch fabric chip is provided for use in different arrangements of fabric interfacing a cell body memory to N input ports and N output ports. Each port has a plurality of lines over which constituent bits of a cell body can be transferred by a succession of bit shifts. The chip includes M externally-accessible, separate memory buses each with an associated plurality S of shift register blocks. Each shift register block has an input shift register of L elements into which bits can be shifted from an input port line, the input shift register being connected to said input contact to enable bits to be shifted into the register, and an output shift register of L elements out of which bits can be shifted through an output port line. The input shift register can transfer its contents in a parallel transfer onto the associated bus and, similarly, the output shift register can be loaded by a parallel transfer from the bus. The chip can handle BM sets of port lines where B is the integer part of the result of the division S/N and where each set includes all corresponding lines taken one from each of the N input and N output ports. Thus, for example, if M=2 and S=8, the chip can be used for switch fabric arrangements with 1, 2, 4 or 8 ports to handle 16, 8, 4, or 2 sets of port lines.
    • 提供了一种单元交换结构芯片,用于将单元体存储器与N个输入端口和N个输出端口对接的结构的不同布置。 每个端口具有多个线,单元主体的组成位可以通过多个行通过一系列位移而被传送。 该芯片包括M个外部可访问的单独的存储器总线,每个存储器总线具有相关联的多个移位寄存器块。 每个移位寄存器块具有一个L个元件的输入移位寄存器,其中位可以从输入端口线移位,输入移位寄存器连接到所述输入触点,以使位能够移入寄存器,以及输出移位寄存器 其中可以通过输出端口线移位位元素。 输入移位寄存器可以将并行传输的内容传送到相关联的总线上,类似地,输出移位寄存器可以通过总线的并行传输进行加载。 芯片可以处理BM组的端口线,其中B是分割结果S / N的整数部分,其中每组包括从N个输入端口和N个输出端口中的每一个中取出一个的所有相应线路。 因此,例如,如果M = 2和S = 8,则芯片可以用于具有1,2,4或8个端口的交换结构布置,以处理16,8,4或2组端口线。
    • 40. 发明授权
    • Motor control for slow speed tape recorder
    • 慢速录音机的电机控制
    • US4213161A
    • 1980-07-15
    • US956829
    • 1978-11-02
    • Edwin A. DokusDavid Banks
    • Edwin A. DokusDavid Banks
    • H02P27/06A61B5/0436G11B15/46G11B15/48G11B25/06G11B19/02
    • G11B25/06A61B5/0436G11B15/46
    • An improved control is provided for the tape transport motor of a battery-powered, slow-speed tape recorder typically used for producing magnetic recordings of an ambulatory patient. The recorder's tape transport means is driven by a synchronous AC motor powered from a DC (battery) supply. That DC supply, during normal operation, is voltage regulated to provide desired speed stability. That DC supply is inverted into a square wave DC current in a manner effectively providing a regulated square wave AC at twice the regulated DC voltage. Phase-shifting means connected to the inverter provide a phase-shifted square wave source necessary for the two-phase AC synchronous motor. In an improved mode of control, means are additionally provided for selectively supplying current at full battery voltage, square wave inverted and phase-shifted to the AC synchronous motor in lieu of the regulated supply voltage to provide high torque operation for selected periods of time as during "start-up" or "warm-up".
    • 提供了一种改进的控制,用于通常用于产生移动病人的磁记录的电池供电的慢速磁带录音机的磁带传送电机。 记录仪的磁带传送装置由一个由DC(电池)电源供电的同步交流电机驱动。 在正常运行期间,该直流电源被调压以提供期望的速度稳定性。 该DC电源以有效地提供两倍于调节的DC电压的调节方波AC的方式被反转成方波DC电流。 连接到逆变器的相移装置提供两相交流同步电动机所需的相移方波源。 在改进的控制方式中,还提供了用于以全电池电压(方波反相和相移到AC同步电动机)的方式提供电流来代替调节的电源电压,以在选定的时间段内提供高转矩操作, 在“启动”或“预热”期间。