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31. 发明授权

US06897535B2 Integrated circuit with reverse engineering protection 有权
标题翻译：具有逆向工程保护的集成电路
公开(公告)号：US06897535B2
公开(公告)日：2005-05-24
申请号：US10438689
申请日：2003-05-14
申请人： Lap-Wai Chow , William M. Clark, Jr. , James P. Baukus
发明人： Lap-Wai Chow , William M. Clark, Jr. , James P. Baukus
IPC分类号： H01L23/58 , H01L27/02 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.
摘要翻译：用于伪装集成电路结构的技术和结构。集成电路结构由具有受控轮廓和受控厚度的多层材料形成。在所述多个层之间设置受控厚度的介电材料层，从而使集成电路结构有意无法操作。

32. 发明授权

US06815816B1 Implanted hidden interconnections in a semiconductor device for preventing reverse engineering 失效
标题翻译：在半导体器件中隐藏的互连用于防止逆向工程
公开(公告)号：US06815816B1
公开(公告)日：2004-11-09
申请号：US09696826
申请日：2000-10-25
申请人： William M. Clark, Jr. , James P. Baukus , Lap-Wai Chow
发明人： William M. Clark, Jr. , James P. Baukus , Lap-Wai Chow
IPC分类号： H01L2348
CPC分类号： H01L27/02 , H01L21/743
摘要： A camouflaged interconnection for interconnecting two spaced-apart implanted regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first implanted region forming a conducting channel between the two spaced-apart implanted regions, the conducting channel being of the same common conductivity type and bridging a region between the two spaced-apart regions, and a second implanted region of opposite conductivity to type, the second implanted region being disposed between the two spaced-apart implanted regions of common conductivity type and over lying the conducting channel to camouflage the conducting channel from reverse engineering.
摘要翻译：一种用于在集成电路或器件中互连公共导电类型的两个间隔开的注入区域的伪装互连和其形成方法。伪装的互连包括在两个间隔开的注入区之间形成导电沟道的第一注入区，导电沟具有相同的共同导电类型并桥接两个间隔开的区之间的区域，导电类型，第二注入区域设置在两个间隔开的公共导电类型的注入区域之间，并且躺在导电沟道上以伪造导电沟道以进行逆向工程。

33. 发明授权

US06613661B1 Process for fabricating secure integrated circuit 失效
标题翻译：制造安全集成电路的过程
公开(公告)号：US06613661B1
公开(公告)日：2003-09-02
申请号：US09607009
申请日：2000-06-29
申请人： James P. Baukus , William M. Clark, Jr. , Lap-Wai Chow , Allan R. Kramer
发明人： James P. Baukus , William M. Clark, Jr. , Lap-Wai Chow , Allan R. Kramer
IPC分类号： H01L2144
CPC分类号： H01L23/573 , G11C7/24 , H01L27/02 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.
摘要翻译：通过将类似导电性的掺杂电路元件与衬底中的掺杂注入相连而不是金属化互连来保护集成电路免于逆向工程。掺杂电路元件及其对应的注入互连可以在具有公共注入掩模的公共制造步骤中形成，使得它们具有类似掺杂剂浓度的整体结构。衬底表面之上的金属化可被设计成提供互连的进一步屏蔽，并且微桥可以被添加到在互连路径中跨越晶体管栅极材料的条带。

34. 发明授权

US06459629B1 Memory with a bit line block and/or a word line block for preventing reverse engineering 有权
标题翻译：具有位线块和/或字线块的存储器用于防止逆向工程
公开(公告)号：US06459629B1
公开(公告)日：2002-10-01
申请号：US09848564
申请日：2001-05-03
申请人： William M. Clark, Jr. , James P. Baukus , Lap-Wai Chow
发明人： William M. Clark, Jr. , James P. Baukus , Lap-Wai Chow
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C7/12 , G11C7/24 , G11C16/22 , H01L27/02
摘要： A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.
摘要翻译：一种用于阻止未经授权的访问半导体存储器中的至少一个存储单元的方法和电路。该方法包括提供在要阻止对至少一个存储器单元的访问时呈现打开状态的开关和/或链接; 以及响应于所述开关或链路假定为打开状态，将与所述至少一个存储器单元相关联的数据线耦合到恒定电压源。

35. 发明授权

US5973375A Camouflaged circuit structure with step implants 失效
标题翻译：具有步进式植入物的伪装电路结构
公开(公告)号：US5973375A
公开(公告)日：1999-10-26
申请号：US869524
申请日：1997-06-06
申请人： James P. Baukus , Lap-Wai Chow , William M. Clark, Jr.
发明人： James P. Baukus , Lap-Wai Chow , William M. Clark, Jr.
IPC分类号： H01L21/74 , H01L27/02 , H01L29/78
CPC分类号： H01L21/743 , H01L27/02 , H01L2924/0002
摘要： Connections between implanted regions in a semiconductor substrate, such as the sources or drains of adjacent transistors, are made by buried conductive implants rather than upper level metalizations. The presence or absence of a connection between two implanted regions is camouflaged by implanting a conductive buried layer of the same doping conductivity as the implanted regions when a connection is desired, and a field implant of opposite conductivity to the implanted regions when no connection is desired, and forming steps into the substrate at the boundaries of the buried layer or field implant that mask the steps formed between different conductivity regions during a selective etch by a reverse engineer. The masking steps are preferably formed by field oxide layers that terminate at the boundaries of the buried layers and field implants.
摘要翻译：半导体衬底中的注入区域（例如相邻晶体管的源极或漏极）之间的连接通过掩埋导电植入而不是上层金属化而制成。当需要连接时，通过注入与注入区相同的掺杂电导率的导电掩埋层和当不需要连接时与注入区相反的导电性的场注入来伪装两个注入区之间的连接的存在或不存在，并且在掩模层或场注入的边界处，在通过反向工程师进行选择性蚀刻期间掩蔽形成在不同导电区域之间的步骤的步骤，形成步骤。掩蔽步骤优选由终止于掩埋层和场植入物的边界的场氧化物层形成。

36. 发明申请

US20120144205A1 Cryptographic Architecture with Instruction Masking and other Techniques for Thwarting Differential Power Analysis 审中-公开
标题翻译：具有指令掩码和其他技术的加密体系结构，用于阻止差分功率分析
公开(公告)号：US20120144205A1
公开(公告)日：2012-06-07
申请号：US13296740
申请日：2011-11-15
申请人： David B. Shu , Lap-Wai Chow , William Clark, JR.
发明人： David B. Shu , Lap-Wai Chow , William Clark, JR.
IPC分类号： G06F21/00
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30181 , G06F9/321 , G06F9/3836 , G06F21/72 , G06F21/755 , G06F21/85 , G06F2221/2123 , H04L9/003 , H04L9/0625 , H04L2209/08 , H04L2209/12
摘要： An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.
摘要翻译：一种用于防止利用时间线对准的信息泄漏攻击的装置和方法。该装置和方法将随机数量的指令插入到加密算法中，使得泄露的信息不能及时对准以允许攻击者中断加密。

37. 发明授权

US08095993B2 Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysis 有权
标题翻译：具有指令掩码和其他技术的加密架构，用于阻止差分功率分析
公开(公告)号：US08095993B2
公开(公告)日：2012-01-10
申请号：US11628920
申请日：2005-06-07
申请人： David B. Shu , Lap-Wai Chow , William Clark, Jr.
发明人： David B. Shu , Lap-Wai Chow , William Clark, Jr.
IPC分类号： G06F11/00
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30181 , G06F9/321 , G06F9/3836 , G06F21/72 , G06F21/75 , G06F21/755 , G06F21/85 , G06F2221/2123 , H04L9/003 , H04L9/0625 , H04L2209/08 , H04L2209/12
摘要： An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.
摘要翻译：一种用于防止利用时间线对准的信息泄漏攻击的装置和方法。该装置和方法将随机数量的指令插入到加密算法中，使得泄露的信息不能及时对准以允许攻击者中断加密。

38. 发明授权

US5928350A Wide memory architecture vector processor using nxP bits wide memory bus for transferring P n-bit vector operands in one cycle 失效
标题翻译：宽存储器架构矢量处理器，使用nxP位宽的存储器总线，用于在一个周期内传输P n位向量操作数
公开(公告)号：US5928350A
公开(公告)日：1999-07-27
申请号：US840178
申请日：1997-04-11
申请人： David B. Shu , David A. Schwartz , Lap-Wai Chow
发明人： David B. Shu , David A. Schwartz , Lap-Wai Chow
IPC分类号： G06F9/30 , G06F9/38 , G06F15/78 , G06F9/312
CPC分类号： G06F15/8069 , G06F9/30141 , G06F9/3826 , G06F9/3885 , G06F9/3887
摘要： A wide memory architecture is provided for storing data associated with a vector processor. Additionally, a method for accessing a wide memory architecture is provided. The wide memory architecture includes a memory for storing an array of vector operands. The memory is coupled to a data bus which provides an access pathway connecting the memory to a processor. The wide memory architecture further includes at least one staging buffer disposed between the memory and the processor. The staging buffer is capable of providing intermediate storage of a vector operand upon which a function can be performed by the processor.
摘要翻译：提供了用于存储与矢量处理器相关联的数据的宽存储器架构。另外，提供了用于访问宽存储器架构的方法。宽存储器架构包括用于存储向量操作数的阵列的存储器。存储器耦合到数据总线，数据总线提供将存储器连接到处理器的访问路径。宽的存储器架构还包括设置在存储器和处理器之间的至少一个分级缓冲器。分段缓冲器能够提供向量操作数的中间存储器，由此可以由处理器执行功能。

39. 发明申请

US20070180541A1 Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysis 有权
标题翻译：具有指令掩码和其他技术的加密架构，用于阻止差分功率分析
公开(公告)号：US20070180541A1
公开(公告)日：2007-08-02
申请号：US11628920
申请日：2005-06-07
申请人： David Shu , Lap-Wai Chow , William Clark
发明人： David Shu , Lap-Wai Chow , William Clark
IPC分类号： G06F11/00
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30181 , G06F9/321 , G06F9/3836 , G06F21/72 , G06F21/75 , G06F21/755 , G06F21/85 , G06F2221/2123 , H04L9/003 , H04L9/0625 , H04L2209/08 , H04L2209/12
摘要： An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.
摘要翻译：一种用于防止利用时间线对准的信息泄漏攻击的装置和方法。该装置和方法将随机数量的指令插入到加密算法中，使得泄露的信息不能及时对准以允许攻击者中断加密。

40. 发明授权

US06367063B1 Method and apparatus for selectively performing a plurality of logic operations and memory functions 失效
标题翻译：用于选择性地执行多个逻辑运算和存储器功能的方法和装置
公开(公告)号：US06367063B1
公开(公告)日：2002-04-02
申请号：US09019069
申请日：1998-02-05
申请人： John A. Harding , David A. Schwartz , Lap-Wai Chow
发明人： John A. Harding , David A. Schwartz , Lap-Wai Chow
IPC分类号： C06F1750
CPC分类号： G06F15/7867
摘要： A logic device for performing a plurality of logic functions employs a plurality of logic elements interconnected by a plurality of switching boxes. A set of configuration bits are provided to the logic. The configuration bits represent a logic circuit that has been partitioned into two or more contexts. A subset of the configuration bits representing the portion of the logic circuit to be performed is selected by a number of context input lines. Operand bits are also provided to the logic element. By using virtualization registers, the output of a logic element in one context can be used as an input in another context. The output for a logic function is selected by the operands and stored in a register bank in such a way that it may later be retrieved by the context number it is associated with.
摘要翻译：用于执行多个逻辑功能的逻辑装置采用由多个开关盒互连的多个逻辑元件。一组配置位提供给逻辑。配置位表示已被划分为两个或多个上下文的逻辑电路。表示要执行的逻辑电路的部分的配置位的子集由多个上下文输入行选择。操作数位也提供给逻辑元件。通过使用虚拟化寄存器，一个上下文中的逻辑元素的输出可以用作另一个上下文中的输入。用于逻辑功能的输出由操作数选择并存储在寄存器组中，使得其随后可以通过与其相关联的上下文编号来检索。

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