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1. 发明申请

US20120144205A1 Cryptographic Architecture with Instruction Masking and other Techniques for Thwarting Differential Power Analysis 审中-公开
标题翻译：具有指令掩码和其他技术的加密体系结构，用于阻止差分功率分析
公开(公告)号：US20120144205A1
公开(公告)日：2012-06-07
申请号：US13296740
申请日：2011-11-15
申请人： David B. Shu , Lap-Wai Chow , William Clark, JR.
发明人： David B. Shu , Lap-Wai Chow , William Clark, JR.
IPC分类号： G06F21/00
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30181 , G06F9/321 , G06F9/3836 , G06F21/72 , G06F21/755 , G06F21/85 , G06F2221/2123 , H04L9/003 , H04L9/0625 , H04L2209/08 , H04L2209/12
摘要： An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.
摘要翻译：一种用于防止利用时间线对准的信息泄漏攻击的装置和方法。该装置和方法将随机数量的指令插入到加密算法中，使得泄露的信息不能及时对准以允许攻击者中断加密。

2. 发明授权

US08095993B2 Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysis 有权
标题翻译：具有指令掩码和其他技术的加密架构，用于阻止差分功率分析
公开(公告)号：US08095993B2
公开(公告)日：2012-01-10
申请号：US11628920
申请日：2005-06-07
申请人： David B. Shu , Lap-Wai Chow , William Clark, Jr.
发明人： David B. Shu , Lap-Wai Chow , William Clark, Jr.
IPC分类号： G06F11/00
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30181 , G06F9/321 , G06F9/3836 , G06F21/72 , G06F21/75 , G06F21/755 , G06F21/85 , G06F2221/2123 , H04L9/003 , H04L9/0625 , H04L2209/08 , H04L2209/12
摘要： An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.
摘要翻译：一种用于防止利用时间线对准的信息泄漏攻击的装置和方法。该装置和方法将随机数量的指令插入到加密算法中，使得泄露的信息不能及时对准以允许攻击者中断加密。

3. 发明授权

US08065532B2 Cryptographic architecture with random instruction masking to thwart differential power analysis 有权
标题翻译：具有随机指令掩码的加密架构，以阻止差分功率分析
公开(公告)号：US08065532B2
公开(公告)日：2011-11-22
申请号：US10864569
申请日：2004-06-08
申请人： David B. Shu , Lap-Wai Chow , William M. Clark, Jr.
发明人： David B. Shu , Lap-Wai Chow , William M. Clark, Jr.
IPC分类号： G06F11/30 , G06F12/14
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30181 , G06F9/321 , G06F9/3836 , G06F21/72 , G06F21/75 , G06F21/755 , G06F21/85 , G06F2221/2123 , H04L9/003 , H04L9/0625 , H04L2209/08 , H04L2209/12
摘要： An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.
摘要翻译：一种用于防止利用时间线对准的信息泄漏攻击的装置和方法。该装置和方法将随机数量的指令插入到加密算法中，使得泄露的信息不能及时对准以允许攻击者中断加密。

4. 发明授权

US07949883B2 Cryptographic CPU architecture with random instruction masking to thwart differential power analysis 有权
标题翻译：具有随机指令掩码的加密CPU架构，以阻止差分功率分析
公开(公告)号：US07949883B2
公开(公告)日：2011-05-24
申请号：US10864568
申请日：2004-06-08
申请人： David B. Shu , Lap-Wai Chow , William M. Clark, Jr.
发明人： David B. Shu , Lap-Wai Chow , William M. Clark, Jr.
IPC分类号： G06F11/30 , G06F12/14
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30181 , G06F9/321 , G06F9/3836 , G06F21/72 , G06F21/75 , G06F21/755 , G06F21/85 , G06F2221/2123 , H04L9/003 , H04L9/0625 , H04L2209/08 , H04L2209/12
摘要： An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.
摘要翻译：一种用于防止利用时间线对准的信息泄漏攻击的装置和方法。该装置和方法将随机数量的指令插入到加密算法中，使得泄露的信息不能及时对准以允许攻击者中断加密。

5. 发明授权

US08296577B2 Cryptographic bus architecture for the prevention of differential power analysis 失效
标题翻译：加密总线架构，用于防止差分功率分析
公开(公告)号：US08296577B2
公开(公告)日：2012-10-23
申请号：US10864556
申请日：2004-06-08
申请人： David B. Shu , Lap-Wai Chow , William M. Clark, Jr.
发明人： David B. Shu , Lap-Wai Chow , William M. Clark, Jr.
IPC分类号： H04L9/00
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30181 , G06F9/321 , G06F9/3836 , G06F21/72 , G06F21/75 , G06F21/755 , G06F21/85 , G06F2221/2123 , H04L9/003 , H04L9/0625 , H04L2209/08 , H04L2209/12
摘要： An apparatus and method for preventing information leakage attacks through a polarized cryptographic bus architecture. The polarized cryptographic bus architecture randomly changes the polarity of the target bit such that the leaked information cannot be consistently averaged to yield statistical key material. Further, to increase the prevention of information leakage attacks, a set of dual rails is used to write data to a given register bit.
摘要翻译：一种用于通过偏振加密总线架构来防止信息泄漏攻击的装置和方法。偏振加密总线结构随机改变目标位的极性，使得泄露的信息不能被一致地平均以产生统计密钥材料。此外，为了增加信息泄露攻击的防范，使用一组双轨将数据写入给定的寄存器位。

6. 发明授权

US5928350A Wide memory architecture vector processor using nxP bits wide memory bus for transferring P n-bit vector operands in one cycle 失效
标题翻译：宽存储器架构矢量处理器，使用nxP位宽的存储器总线，用于在一个周期内传输P n位向量操作数
公开(公告)号：US5928350A
公开(公告)日：1999-07-27
申请号：US840178
申请日：1997-04-11
申请人： David B. Shu , David A. Schwartz , Lap-Wai Chow
发明人： David B. Shu , David A. Schwartz , Lap-Wai Chow
IPC分类号： G06F9/30 , G06F9/38 , G06F15/78 , G06F9/312
CPC分类号： G06F15/8069 , G06F9/30141 , G06F9/3826 , G06F9/3885 , G06F9/3887
摘要： A wide memory architecture is provided for storing data associated with a vector processor. Additionally, a method for accessing a wide memory architecture is provided. The wide memory architecture includes a memory for storing an array of vector operands. The memory is coupled to a data bus which provides an access pathway connecting the memory to a processor. The wide memory architecture further includes at least one staging buffer disposed between the memory and the processor. The staging buffer is capable of providing intermediate storage of a vector operand upon which a function can be performed by the processor.
摘要翻译：提供了用于存储与矢量处理器相关联的数据的宽存储器架构。另外，提供了用于访问宽存储器架构的方法。宽存储器架构包括用于存储向量操作数的阵列的存储器。存储器耦合到数据总线，数据总线提供将存储器连接到处理器的访问路径。宽的存储器架构还包括设置在存储器和处理器之间的至少一个分级缓冲器。分段缓冲器能够提供向量操作数的中间存储器，由此可以由处理器执行功能。

7. 发明申请

US20090170255A1 INTEGRATED CIRCUIT MODIFICATION USING WELL IMPLANTS 失效
标题翻译：使用良好的植入物进行集成电路修改
公开(公告)号：US20090170255A1
公开(公告)日：2009-07-02
申请号：US12399628
申请日：2009-03-06
申请人： Lap-Wai Chow , William M. Clark, JR. , James P. Baukus , Gavin J. Harbison
发明人： Lap-Wai Chow , William M. Clark, JR. , James P. Baukus , Gavin J. Harbison
IPC分类号： H01L21/8238
CPC分类号： H01L21/823892 , H01L27/02
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
摘要翻译：用于伪装集成电路结构的技术和结构。集成电路结构形成为具有第一导电类型的阱，栅极区域邻近第一导电类型的有源区设置。该阱在有源区域之间形成电路径，而不管施加到集成电路结构的任何合理的电压。

8. 发明申请

US20070180541A1 Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysis 有权
标题翻译：具有指令掩码和其他技术的加密架构，用于阻止差分功率分析
公开(公告)号：US20070180541A1
公开(公告)日：2007-08-02
申请号：US11628920
申请日：2005-06-07
申请人： David Shu , Lap-Wai Chow , William Clark
发明人： David Shu , Lap-Wai Chow , William Clark
IPC分类号： G06F11/00
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30181 , G06F9/321 , G06F9/3836 , G06F21/72 , G06F21/75 , G06F21/755 , G06F21/85 , G06F2221/2123 , H04L9/003 , H04L9/0625 , H04L2209/08 , H04L2209/12
摘要： An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.
摘要翻译：一种用于防止利用时间线对准的信息泄漏攻击的装置和方法。该装置和方法将随机数量的指令插入到加密算法中，使得泄露的信息不能及时对准以允许攻击者中断加密。

9. 发明授权

US06740942B2 Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact 失效
标题翻译：永久性地使用采用双重多晶硅层CMOS工艺的埋入触点实现晶体管
公开(公告)号：US06740942B2
公开(公告)日：2004-05-25
申请号：US09882892
申请日：2001-06-15
申请人： James P. Baukus , Lap-Wai Chow , William M. Clark, Jr.
发明人： James P. Baukus , Lap-Wai Chow , William M. Clark, Jr.
IPC分类号： H01L2976
CPC分类号： H01L27/0203 , H01L21/76895 , H01L21/823462 , H01L23/576 , H01L27/0883 , H01L29/7834 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.
摘要翻译：永久导通MOS晶体管包括在第二导电类型的硅阱区域中的第一导电类型的硅源极和漏极区域。所述第一导电类型的硅接触区域埋在所述阱区域中，所述接触区域接触所述源极区域和所述漏极区域。选择性地将第一栅极绝缘层放置在硅源极和漏极区域上。第二栅极绝缘层选择性地放置在第一栅极绝缘层上方和硅接触区域上。多晶硅栅极区域放置在第二栅极绝缘层上。

10. 发明授权

US06367063B1 Method and apparatus for selectively performing a plurality of logic operations and memory functions 失效
标题翻译：用于选择性地执行多个逻辑运算和存储器功能的方法和装置
公开(公告)号：US06367063B1
公开(公告)日：2002-04-02
申请号：US09019069
申请日：1998-02-05
申请人： John A. Harding , David A. Schwartz , Lap-Wai Chow
发明人： John A. Harding , David A. Schwartz , Lap-Wai Chow
IPC分类号： C06F1750
CPC分类号： G06F15/7867
摘要： A logic device for performing a plurality of logic functions employs a plurality of logic elements interconnected by a plurality of switching boxes. A set of configuration bits are provided to the logic. The configuration bits represent a logic circuit that has been partitioned into two or more contexts. A subset of the configuration bits representing the portion of the logic circuit to be performed is selected by a number of context input lines. Operand bits are also provided to the logic element. By using virtualization registers, the output of a logic element in one context can be used as an input in another context. The output for a logic function is selected by the operands and stored in a register bank in such a way that it may later be retrieved by the context number it is associated with.
摘要翻译：用于执行多个逻辑功能的逻辑装置采用由多个开关盒互连的多个逻辑元件。一组配置位提供给逻辑。配置位表示已被划分为两个或多个上下文的逻辑电路。表示要执行的逻辑电路的部分的配置位的子集由多个上下文输入行选择。操作数位也提供给逻辑元件。通过使用虚拟化寄存器，一个上下文中的逻辑元素的输出可以用作另一个上下文中的输入。用于逻辑功能的输出由操作数选择并存储在寄存器组中，使得其随后可以通过与其相关联的上下文编号来检索。

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