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31. 发明申请

US20050118757A1 Method for integration of silicide contacts and silicide gate metals 失效
标题翻译：硅化物触点和硅化物栅极金属的集成方法
公开(公告)号：US20050118757A1
公开(公告)日：2005-06-02
申请号：US10725851
申请日：2003-12-02
申请人： Cyril Cabral , Jakub Kedzierski , Victor Ku , Christian Lavoie , Vijay Narayanan , An Steegen
发明人： Cyril Cabral , Jakub Kedzierski , Victor Ku , Christian Lavoie , Vijay Narayanan , An Steegen
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823835
摘要： A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated in fabricating a CMOS structure containing silicide contacts and silicide gate metals.
摘要翻译：提供了允许使用自对准工艺（自对准硅化物）以及一个或多个光刻步骤并入硅化物触点（S / D和栅极）和金属硅化物栅极的CMOS硅化物金属集成方案。本发明的集成方案最小化了制造包含硅化物触点和硅化物栅极金属的CMOS结构所涉及的复杂性和成本。

32. 发明申请

US20050104142A1 CVD tantalum compounds for FET get electrodes 审中-公开
标题翻译：用于FET的CVD钽化合物获得电极
公开(公告)号：US20050104142A1
公开(公告)日：2005-05-19
申请号：US10712575
申请日：2003-11-13
申请人： Vijav Narayanan , Fenton McFeely , Keith Milkove , John Yurkas , Matthew Copel , Paul Jamison , Roy Carruthers , Cyril Cabral , Edmund Sikorskii , Elizabeth Duch , Alessandro Callegari , Sufi Zafar , Kazuhito Nakamura
发明人： Vijav Narayanan , Fenton McFeely , Keith Milkove , John Yurkas , Matthew Copel , Paul Jamison , Roy Carruthers , Cyril Cabral , Edmund Sikorskii , Elizabeth Duch , Alessandro Callegari , Sufi Zafar , Kazuhito Nakamura
IPC分类号： C23C16/34 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/10 , H01L29/49 , H01L29/772 , H01L29/78 , H01L29/76
CPC分类号： C23C16/34 , H01L21/28088 , H01L21/823828 , H01L29/4966 , H01L29/78
摘要： Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20 mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta—N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta—N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.
摘要翻译：公开了Ta和N的化合物，潜在地包括其它元素，并且电阻率低于约20mOmegacm，并且N与Ta的元素比大于约0.9，用作场效应器件中的栅极材料。这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下在含有介电层和高k电介质层的SiO 2 2上是稳定的，功函数接近n型Si的功函数。金属Ta-N化合物通过化学气相沉积方法使用烷基亚氨基三（二烷基酰氨基）Ta种，例如叔戊酰亚胺基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。用TaN或TaSiN处理的器件显示出接近理想的特性。

33. 发明申请

US20050064690A1 PROCESS OPTIONS OF FORMING SILICIDED METAL GATES FOR ADVANCED CMOS DEVICES 失效
标题翻译：用于高级CMOS器件形成硅化金属栅的工艺选择
公开(公告)号：US20050064690A1
公开(公告)日：2005-03-24
申请号：US10605261
申请日：2003-09-18
申请人： Ricky Amos , Douglas Buchanan , Cyril Cabral , Evgeni Gousev , Victor Ku , An Steegen
发明人： Ricky Amos , Douglas Buchanan , Cyril Cabral , Evgeni Gousev , Victor Ku , An Steegen
IPC分类号： H01L21/768 , H01L21/8238 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823835
摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.
摘要翻译：硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或现有的金属门。硅化物用作连接CMOS结构的PFET和NFET器件的选项。该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。提供了具有栅极和源极和漏极区域的半导体衬底。栅极电介质层与金属栅极层一起沉积在衬底上。然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。可以在栅极内使用第二硅化物。在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

34. 发明申请

US20050059242A1 Reduction of silicide formation temperature on SiGe containing substrates 有权
标题翻译：在含SiGe的基板上降低硅化物的形成温度
公开(公告)号：US20050059242A1
公开(公告)日：2005-03-17
申请号：US10662900
申请日：2003-09-15
申请人： Cyril Cabral , Roy Carruthers , Christophe Detavernier , James Harper , Christian Lavoie
发明人： Cyril Cabral , Roy Carruthers , Christophe Detavernier , James Harper , Christian Lavoie
IPC分类号： H01L21/285 , H01L21/44 , H01L29/76
CPC分类号： H01L21/28518
摘要： A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.
摘要翻译：提供了一种解决在锗原子存在下形成二硅化钴期间显示的增加的成核温度的方法。硅化物形成温度的降低通过首先提供包括至少包含Ni的Co层作为添加元素在包含SiGe的衬底的顶部上的结构来实现。接下来，对该结构进行自对准硅化物工艺，其包括第一退火，选择性蚀刻步骤和第二退火，以在含SiGe的衬底上形成（Co，Ni）二硅化物的固溶体。至少包括Ni的Co层可以包括Co和Ni的合金层，Ni / Co的堆叠或Co / Ni的堆叠。还提供了包含（Co，Ni）二硅化物在含SiGe的衬底上的固溶体的半导体结构。

35. 发明申请

US20080274611A1 METHOD AND PROCESS FOR FORMING A SELF-ALIGNED SILICIDE CONTACT 有权
标题翻译：形成自对准硅酮接触的方法和工艺
公开(公告)号：US20080274611A1
公开(公告)日：2008-11-06
申请号：US12136885
申请日：2008-06-11
申请人： Cyril Cabral , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
发明人： Cyril Cabral , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.
摘要翻译：本发明提供一种形成自对准Ni合金硅化物接触的方法。本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金，整个半导体结构，其包括至少一个栅极堆叠区域。包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。与诸如SiO 2和Si 3 N 4 N之类的绝缘材料直接接触的金属在金属合金硅化物接触期间不会转化为金属合金硅化物接触然后执行退火步骤A选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

36. 发明申请

US20080254622A1 CMOS SILICIDE METAL GATE INTEGRATION 失效
标题翻译： CMOS硅胶金属门整合
公开(公告)号：US20080254622A1
公开(公告)日：2008-10-16
申请号：US12145113
申请日：2008-06-24
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

37. 发明申请

US20080246120A1 REDUCTION OF SILICIDE FORMATION TEMPERATURE ON SiGe CONTAINING SUBSTRATES 有权
标题翻译：在含SiGe衬底上减少硅化物形成温度
公开(公告)号：US20080246120A1
公开(公告)日：2008-10-09
申请号：US12120854
申请日：2008-05-15
申请人： Cyril Cabral , Roy A. Carruthers , Jia Chen , Christophe Detavernier , James M. Harper , Christian Lavoie
发明人： Cyril Cabral , Roy A. Carruthers , Jia Chen , Christophe Detavernier , James M. Harper , Christian Lavoie
IPC分类号： H01L29/161
CPC分类号： H01L21/28518
摘要： A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.
摘要翻译：提供了一种解决在锗原子存在下形成二硅化钴期间显示的增加的成核温度的方法。硅化物形成温度的降低通过首先提供包括至少包含Ni的Co层作为添加元素在包含SiGe的衬底的顶部上的结构来实现。接下来，对该结构进行自对准硅化物工艺，其包括第一退火，选择性蚀刻步骤和第二退火，以在含SiGe的衬底上形成（Co，Ni）二硅化物的固溶体。至少包括Ni的Co层可以包括Co和Ni的合金层，Ni / Co的堆叠或Co / Ni的堆叠。还提供了包含（Co，Ni）二硅化物在含SiGe的衬底上的固溶体的半导体结构。

38. 发明申请

US20080227283A1 SELF-ALIGNED METAL TO FORM CONTACTS TO Ge CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY 失效
标题翻译：自对准金属形成与包含基体的结构和形成的结构
公开(公告)号：US20080227283A1
公开(公告)日：2008-09-18
申请号：US12108001
申请日：2008-04-23
申请人： Cyril Cabral , Roy A. Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
发明人： Cyril Cabral , Roy A. Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
IPC分类号： H01L21/28
CPC分类号： H01L21/28525 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming gennano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.
摘要翻译：提供了一种在与由纯金属形成的常规硅化物接触相比更耐蚀刻性的Ge含有层上方形成硅锗化物的方法。本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。在暴露的区域中，含Ge衬底与含Si金属层接触。然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。在一些实施方案中，附加的退火步骤可以跟随去除步骤。本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

39. 发明申请

US20080220581A1 OPTO-THERMAL ANNEALING METHODS FOR FORMING METAL GATE AND FULLY SILICIDED GATE-FIELD EFFECT TRANSISTORS 有权
标题翻译：用于形成金属门和完全硅化的栅极效应晶体管的光热退火方法
公开(公告)号：US20080220581A1
公开(公告)日：2008-09-11
申请号：US12120286
申请日：2008-05-14
申请人： Scott D. Allen , Cyril Cabral , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

40. 发明申请

US20070034967A1 METAL GATE MOSFET BY FULL SEMICONDUCTOR METAL ALLOY CONVERSION 审中-公开
标题翻译：金属栅MOSFET通过全半导体金属合金转换
公开(公告)号：US20070034967A1
公开(公告)日：2007-02-15
申请号：US11537718
申请日：2006-10-02
申请人： Hasan Nayfeh , Mahender Kumar , Sunfei Fang , Jakub Kedzierski , Cyril Cabral
发明人： Hasan Nayfeh , Mahender Kumar , Sunfei Fang , Jakub Kedzierski , Cyril Cabral
IPC分类号： H01L29/94
CPC分类号： H01L21/823835 , H01L21/823842 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.
摘要翻译：描述了MOSFET结构和形成方法。该方法包括形成足够厚的含金属层，以将半导体栅极堆叠完全转换成第一MOSFET型区域中的半导体金属合金，但是仅仅足够厚以将第二半导体栅极堆叠部分地转换为半导体金属合金 MOSFET类型区域。在一个实施例中，在形成含金属层之前，第一MOSFET区域中的栅极堆叠是凹进的，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。在另一个实施例中，在转换过程之前，含金属层相对于另一个MOSFET区域在一个MOSFET区域上变薄。

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