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31. 发明授权

US07397702B2 Read/verify circuit for multilevel memory cells with ramp read voltage, and read/verify method thereof 有权
标题翻译：具有斜坡读取电压的多电平存储单元的读取/验证电路及其读取/验证方法
公开(公告)号：US07397702B2
公开(公告)日：2008-07-08
申请号：US11178240
申请日：2005-07-08
申请人： Paolo Rolandi , Luigi Pascucci
发明人： Paolo Rolandi , Luigi Pascucci
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5642 , G11C16/28 , G11C16/3454 , G11C16/3459 , G11C2211/5634
摘要： A read/verify circuit for multilevel memory cells includes: a read terminal selectively connectable to a plurality of array cells, having respective array threshold voltages; a plurality of reference cells, having respective reference threshold voltages; and a plurality of threshold-detection circuits, for detecting the array thresholds and the reference thresholds. In particular, the read terminal and the reference cells are each connected to a respective threshold-detection circuit. Each threshold-detection circuit is provided with a respective detector element of a resistive type, set so as to be traversed by a current response to turning-on of the respective array cell or reference cell associated thereto.
摘要翻译：用于多电平存储器单元的读/验电路包括：可选择地连接到具有相应阵列阈值电压的多个阵列单元的读终端; 多个参考单元，具有各自的参考阈值电压; 以及用于检测阵列阈值和参考阈值的多个阈值检测电路。特别地，读取终端和参考单元各自连接到相应的阈值检测电路。每个阈值检测电路设置有电阻型的相应检测器元件，其被设置为通过与其相关联的相应阵列单元或参考单元的导通的电流响应来遍历。

32. 发明申请

US20070279996A1 METHOD AND SYSTEM FOR REFRESHING A MEMORY DEVICE DURING READING THEREOF 有权
标题翻译：在读取存储器件时刷新的方法和系统
公开(公告)号：US20070279996A1
公开(公告)日：2007-12-06
申请号：US11695552
申请日：2007-04-02
申请人： Paolo Rolandi , Luigi Pascucci
发明人： Paolo Rolandi , Luigi Pascucci
IPC分类号： G11C16/06
CPC分类号： G11C16/3431 , G11C11/5628 , G11C16/3418
摘要： A refresh circuit for refreshing a memory device is proposed. The refresh circuit includes: reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells each one having a reference threshold voltage, means for detecting the reaching of a comparison current by a cell current of each memory cell and by a reference current of each reference cell, and means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and the reference currents, and writing means for applying a writing voltage to at least one selected of the memory cells; the refresh circuit further includes control means for enabling the writing means during at least part of the application of the biasing voltage after the determination of the condition of each selected memory cell.
摘要翻译：提出了刷新存储器件的刷新电路。刷新电路包括：用于读取一组存储单元的读取装置，所述读取装置包括用于向存储单元施加具有基本上单调的时间模式的偏置电压的装置和具有参考阈值电压的一组参考单元，用于通过每个存储单元的单元电流和每个参考单元的参考电流来检测比较电流达到的装置，以及用于根据达到比较电流的时间关系确定每个存储单元的状态的装置对应的单元电流和参考电流;以及写入装置，用于向至少一个选择的存储单元施加写入电压; 刷新电路还包括控制装置，用于在确定每个所选择的存储单元的状态之后，在施加偏置电压的至少一部分期间使写入装置能够使能。

33. 发明申请

US20070041263A1 Row decoder circuit for electrically programmable and erasable non volatile memories 有权
标题翻译：行解码器电路，用于电可编程和可擦除非易失性存储器
公开(公告)号：US20070041263A1
公开(公告)日：2007-02-22
申请号：US11504539
申请日：2006-08-14
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C16/16
摘要： The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity emulating at least 16 kB and even overcoming by at least 2 kB Flash memories of the NAND type. The memory can thus maintain high performances in terms of random access speed but shows a high erasing speed typical of memory architectures of the NAND type.
摘要翻译：本发明涉及一种用于电可编程和可擦除类型的非易失性存储器件的行解码器电路，例如具有NOR架构的闪速EEPROM类型。所提出的行解码器电路允许非常快速地执行擦除步骤，例如，以至少16kB的粒度并且甚至由NAND类型的至少2kB的闪存来克服的粒度。因此，存储器可以在随机访问速度方面保持高性能，但是显示出NAND类型的存储器架构的典型的高擦除速度。

34. 发明申请

US20060268650A1 Row decoder circuit and related system and method 有权
公开(公告)号：US20060268650A1
公开(公告)日：2006-11-30
申请号：US11434564
申请日：2006-05-15
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C16/08
摘要： A row decoder circuit is described of the type comprising at least one input stage connected to a first supply voltage reference and to an output stage connected to a second supply voltage reference, the output stage having at least one output terminal connected to a word line of a memory matrix. The row decoder circuit further comprises a biasing device, connected to a third supply voltage reference and comprising at least one generator of a negative voltage connected to a divider, in turn connected to a first biasing terminal of the biasing device. In particular, the first biasing terminal is connected to at least one input stage in correspondence with bulk terminals of MOS transistors comprised in the input stage and it is suitable for supplying it with a first negative voltage.

35. 发明申请

US20060239076A1 NON-VOLATILE MEMORY ELECTRONIC DEVICE WITH NAND STRUCTURE BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR 有权
标题翻译：具有NAND结构的非易失性存储器件电子器件单一集成在半导体
公开(公告)号：US20060239076A1
公开(公告)日：2006-10-26
申请号：US11279385
申请日：2006-04-11
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
摘要翻译：非易失性存储器电子器件集成在半导体上，并且具有闪存EEPROM类型，其具有NAND架构，其包括分成物理扇区的至少一个存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列或位线的存储单元。给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端行指向源行的相同选择行。

36. 发明授权

US06920066B2 Programming method of the memory cells in a multilevel non-volatile memory device 有权
标题翻译：多级非易失性存储器件中存储单元的编程方法
公开(公告)号：US06920066B2
公开(公告)日：2005-07-19
申请号：US10438175
申请日：2003-05-13
申请人： Luigi Pascucci , Paolo Rolandi , Marco Riva
发明人： Luigi Pascucci , Paolo Rolandi , Marco Riva
IPC分类号： G11C11/56 , G11C16/04
CPC分类号： G11C11/5628
摘要： A method for programming a non-volatile memory device of the multi-level type, includes a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses. Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.
摘要翻译：一种用于对多电平型非易失性存储器件进行编程的方法包括分组成存储字的多个晶体管单元，并且通常设置有栅极和漏极端子。该方法在不同的阈值下应用不同的漏极电压值。这些值与各个存储器字位要达到的阈值水平成正比，并有效地提供了在有限数量的脉冲结束时以寻求方式获得电平的电平。有利地，恒定栅极电压值同时施加到所述单元的栅极端子，使得单元编程时间与所寻求的阈值水平无关。

37. 发明授权

US06816407B2 Method for storing and reading data in a multilevel nonvolatile memory, and architecture therefor 有权
标题翻译：用于在多级非易失性存储器中存储和读取数据的方法及其架构
公开(公告)号：US06816407B2
公开(公告)日：2004-11-09
申请号：US10259252
申请日：2002-09-26
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C1604
CPC分类号： G11C19/282 , G11C11/5628 , G11C11/5642
摘要： According to the multilevel programming method, each memory location can be programmed at a non-binary number of levels. The bits to be stored in the two locations are divided into two sets, wherein the first set defines a number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location; if it is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location. The bits of the first set in the second location are stored in different levels with respect to the bits of the second set.

38. 发明授权

US06549473B2 Circuital structure for reading data in a non-volatile memory device 有权
公开(公告)号：US06549473B2
公开(公告)日：2003-04-15
申请号：US09871234
申请日：2001-05-30
申请人： Paolo Rolandi , Massimo Montanaro , Giorgio Oddone
发明人： Paolo Rolandi , Massimo Montanaro , Giorgio Oddone
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5642 , G11C2211/5634
摘要： A circuit structure for reading data contained in an electrically programmable/erasable integrated non-volatile memory device includes a matrix of memory cells and at least one reference cell for comparison with a memory cell during a reading phase. The reference cell is incorporated in a reference cells sub-matrix which is structurally independent of the matrix of memory cells. Also provided is a conduction path between the matrix and the sub-matrix, which path includes bit lines of the sub-matrix of reference cells extended continuously into the matrix of memory cells.

39. 发明授权

US06476664B2 Integrated device with voltage selector 失效
标题翻译：带电压选择器的集成设备
公开(公告)号：US06476664B2
公开(公告)日：2002-11-05
申请号：US09823262
申请日：2001-03-29
申请人： Paolo Rolandi , Massimo Montanaro , Giorgio Oddone
发明人： Paolo Rolandi , Massimo Montanaro , Giorgio Oddone
IPC分类号： G05F110
CPC分类号： G11C16/12
摘要： The integrated device comprises a PMOS transistor and a voltage selector having an output connected to the bulk terminal of the PMOS transistor. The voltage selector comprises an input stage supplying a supply voltage or a programming voltage according to whether the device is in a reading step or in a programming step; a comparator connected to the output of the input stage, receiving a boosted voltage, and generating a first control signal, the state whereof depends upon the comparison of the voltages at the inputs of the comparator; a logic circuit connected to the output of the comparator and generating a second control signal, the state whereof depends upon the state of the first control signal and of a third-level signal; and a switching circuit controlled by the first control signal, by the second control signal, and by the third-level signal and supplying each time the highest among the supply voltage, the boosted voltage, and the programming voltage.
摘要翻译：集成器件包括PMOS晶体管和具有连接到PMOS晶体管的体端的输出的电压选择器。电压选择器包括输入级，其根据该器件是处于读取步骤还是在编程步骤中提供电源电压或编程电压; 连接到输入级的输出的比较器，接收升高的电压，并产生第一控制信号，其状态取决于比较器输入端的电压的比较; 连接到比较器的输出并产生第二控制信号的逻辑电路，其状态取决于第一控制信号和第三电平信号的状态; 以及由第一控制信号，第二控制信号和第三电平信号控制的开关电路，并且每一时刻提供电源电压，升压电压和编程电压中的最高值。

40. 发明授权

US06438669B2 Timesharing internal bus, particularly for non-volatile memories 失效
标题翻译：分时内部总线，特别适用于非易失性存储器
公开(公告)号：US06438669B2
公开(公告)日：2002-08-20
申请号：US08813687
申请日：1997-03-07
申请人： Luigi Pascucci , Paolo Rolandi , Marco Fontana , Antonio Barcella
发明人： Luigi Pascucci , Paolo Rolandi , Marco Fontana , Antonio Barcella
IPC分类号： G06F1300
CPC分类号： G11C7/1006
摘要： A non-volatile memory device that comprises an internal bus for the transmission of data and other information of the memory to output pads; a timer; and an enabling/disabling circuit for enabling and disabling access to the internal bus; the timer controlling the internal bus to transmit information signals of the memory device that originate from local auxiliary lines over the internal bus when the bus is in an inactive period during a normal memory data reading cycle; the timer controlling the enabling/disabling means to allow/deny access to the internal bus on the part of the information signals or of the data from or to the memory.
摘要翻译：一种非易失性存储器件，包括用于将数据和存储器的其它信息传输到输出焊盘的内部总线; 一个计时器以及用于启用和禁用访问内部总线的启用/禁用电路; 所述定时器控制所述内部总线，以在所述总线在正常存储器数据读取周期期间处于非活动时段期间，通过所述内部总线发送来自所述本地辅助线路的存储器件的信息信号; 所述定时器控制所述启用/禁用装置允许/拒绝部分所述信息信号或来自所述存储器的数据的所述内部总线的访问。

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