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1. 发明授权

US06920066B2 Programming method of the memory cells in a multilevel non-volatile memory device 有权
标题翻译：多级非易失性存储器件中存储单元的编程方法
公开(公告)号：US06920066B2
公开(公告)日：2005-07-19
申请号：US10438175
申请日：2003-05-13
申请人： Luigi Pascucci , Paolo Rolandi , Marco Riva
发明人： Luigi Pascucci , Paolo Rolandi , Marco Riva
IPC分类号： G11C11/56 , G11C16/04
CPC分类号： G11C11/5628
摘要： A method for programming a non-volatile memory device of the multi-level type, includes a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses. Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.
摘要翻译：一种用于对多电平型非易失性存储器件进行编程的方法包括分组成存储字的多个晶体管单元，并且通常设置有栅极和漏极端子。该方法在不同的阈值下应用不同的漏极电压值。这些值与各个存储器字位要达到的阈值水平成正比，并有效地提供了在有限数量的脉冲结束时以寻求方式获得电平的电平。有利地，恒定栅极电压值同时施加到所述单元的栅极端子，使得单元编程时间与所寻求的阈值水平无关。

2. 发明授权

US06301157B1 Method and circuit for testing memory cells in a multilevel memory device 失效
标题翻译：用于测试多电平存储器件中的存储单元的方法和电路
公开(公告)号：US06301157B1
公开(公告)日：2001-10-09
申请号：US09415024
申请日：1999-10-07
申请人： Marco Riva , Paolo Rolandi , Massimo Montanaro
发明人： Marco Riva , Paolo Rolandi , Massimo Montanaro
IPC分类号： G11C1606
CPC分类号： G11C29/50 , G06F2201/81 , G11C11/56 , G11C11/5642 , G11C2029/5006 , G11C2211/5634
摘要： A method for testing memory cells, and in particular virgin memory cells, in a multilevel memory device having a plurality of memory cells. The method includes reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not; determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell; the at least one reference memory cell being chosen with a gradually higher threshold; when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.
摘要翻译：一种用于在具有多个存储器单元的多电平存储器件中测试存储器单元，特别是处理存储器单元的方法。该方法包括读取构成存储器件的各个存储器单元，并且每次将这些存储器单元中的每一个与至少一个参考存储器单元进行比较，以便确定存储器单元的阈值是否低于至少一个参考存储器单元; 确定其阈值高于所述至少一个参考小区的阈值的存储器单元的数量; 所述至少一个参考存储器单元被选择为具有逐渐更高的阈值; 当阈值高于给定参考阈值的存储单元的数量被发现足够低于设置在存储器件中的冗余存储单元的数量时，假定给定参考阈值为存储器件的较低参考阈值，则确定存储单元阈值的统计分布。

3. 发明授权

US08054110B2 Driver circuit for gallium nitride (GaN) heterojunction field effect transistors (HFETs) 有权
标题翻译：氮化镓（GaN）异质结场效应晶体管（HFET）的驱动电路
公开(公告)号：US08054110B2
公开(公告)日：2011-11-08
申请号：US12690495
申请日：2010-01-20
申请人： Bo Wang , Antonello Monti , Jason Bakos , Marco Riva
发明人： Bo Wang , Antonello Monti , Jason Bakos , Marco Riva
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/018521
摘要： A driver circuit and integrated circuit implementation of a driver circuit for driving a GaN HFET device is disclosed. The driver circuit includes a resonant drive circuit having an LC circuit with an inductance and a capacitance. The capacitance of the LC circuit includes the gate-source capacitance of the GaN HFET device. The driver circuit further includes a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal suitable for driving a GaN HFET device. The resonant drive circuit is controlled based at least in part on the second signal such that the resonant drive circuit provides a first voltage to the GaN HFET device to control the GaN HFET device to operate in a conducting state and to provide a second voltage to the GaN HFET device to control the GaN HFET device to operate in a non-conducting state.
摘要翻译：公开了用于驱动GaN HFET器件的驱动电路的驱动电路和集成电路实现。驱动器电路包括具有电感和电容的LC电路的谐振驱动电路。 LC电路的电容包括GaN HFET器件的栅 - 源电容。驱动器电路还包括电平移位器电路，其被配置为接收第一信号并将第一信号放大到适于驱动GaN HFET器件的第二信号。至少部分地基于第二信号来控制谐振驱动电路，使得谐振驱动电路向GaN HFET器件提供第一电压以控制GaN HFET器件工作在导通状态，并向第二电压提供第二电压 GaN HFET器件来控制GaN HFET器件工作在非导通状态。

4. 发明授权

US06788517B2 Conduction line decoupling circuit 有权
标题翻译：导通线去耦电路
公开(公告)号：US06788517B2
公开(公告)日：2004-09-07
申请号：US09917613
申请日：2001-07-26
申请人： Marco Riva
发明人： Marco Riva
IPC分类号： H02H322
CPC分类号： H03K17/162 , H03K17/165
摘要： A decoupling circuit for decoupling conduction lines from each other, the circuit including at least one pass gate element having conduction terminals connected to the conduction lines and having at least one control terminal. The decoupling circuit includes at least one protection circuit inserted between the control terminal and at least one of the conduction lines, and including at least one protection transistor connected to the control terminal and to the at least one conduction line, and configured to take in a disturbing signal passing through the pass gate element (N1) to properly decouple the conduction lines from each other on the occurrence of a disturbing condition.
摘要翻译：一种用于使导线彼此去耦的去耦电路，该电路包括至少一个具有连接到导线并具有至少一个控制端的导通端的通栅元件。去耦电路包括至少一个保护电路，其插入在控制端与至少一个导线之间，并且包括连接到控制端和至少一个导线的至少一个保护晶体管，干扰信号通过通过栅极元件（N1），以便在发生干扰条件时使导线彼此适当地解耦。

5. 发明申请

US20110025397A1 DRIVER CIRCUIT FOR GALLIUM NITRIDE (GaN) HETEROJUNCTION FIELD EFFECT TRANSISTORS (HFETs) 有权
标题翻译：氮化镓（GaN）异质场效应晶体管（HFET）的驱动电路
公开(公告)号：US20110025397A1
公开(公告)日：2011-02-03
申请号：US12690495
申请日：2010-01-20
申请人： Bo Wang , Antonello Monti , Jason Bakos , Marco Riva
发明人： Bo Wang , Antonello Monti , Jason Bakos , Marco Riva
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A driver circuit and integrated circuit implementation of a driver circuit for driving a GaN HFET device is disclosed. The driver circuit includes a resonant drive circuit having an LC circuit with an inductance and a capacitance. The capacitance of the LC circuit includes the gate-source capacitance of the GaN HFET device. The driver circuit further includes a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal suitable for driving a GaN HFET device. The resonant drive circuit is controlled based at least in part on the second signal such that the resonant drive circuit provides a first voltage to the GaN HFET device to control the GaN HFET device to operate in a conducting state and to provide a second voltage to the GaN HFET device to control the GaN HFET device to operate in a non-conducting state.
摘要翻译：公开了用于驱动GaN HFET器件的驱动电路的驱动电路和集成电路实现。驱动器电路包括具有电感和电容的LC电路的谐振驱动电路。 LC电路的电容包括GaN HFET器件的栅 - 源电容。驱动器电路还包括电平移位器电路，其被配置为接收第一信号并将第一信号放大到适于驱动GaN HFET器件的第二信号。至少部分地基于第二信号来控制谐振驱动电路，使得谐振驱动电路向GaN HFET器件提供第一电压以控制GaN HFET器件工作在导通状态，并向第二电压提供第二电压 GaN HFET器件来控制GaN HFET器件工作在非导通状态。

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