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31. 发明授权

US07528022B2 Method of forming fin field effect transistor using damascene process 有权
标题翻译：使用镶嵌工艺形成翅片场效应晶体管的方法
公开(公告)号：US07528022B2
公开(公告)日：2009-05-05
申请号：US11112818
申请日：2005-04-21
申请人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
发明人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7851 , H01L21/26586 , H01L29/66818
摘要： A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part of the upper portion of the fin. A gate electrode is formed to fill the groove with a gate insulation layer interposed between the fin and the gate electrode, and the mold layer is removed. Impurities are implanted through both sidewalls and a top surface of the upper portion of the fin disposed at opposite sides of a gate electrode to form a source/drain region.
摘要翻译：提供了一种使用镶嵌工艺形成鳍式晶体管的方法。填充模具绝缘图案凹入以暴露翅片的上部，并且形成模具层。图案化模具层以形成与散热片交叉的凹槽并暴露翅片上部的一部分。形成栅电极，用插入翅片和栅电极之间的栅极绝缘层填充凹槽，并且去除模层。通过设置在栅极电极的相对侧的翅片的上侧部分的两个侧壁和顶部表面注入杂质以形成源极/漏极区域。

32. 发明申请

US20090065850A1 NON-VOLATILE MEMORY DEVICES 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：US20090065850A1
公开(公告)日：2009-03-12
申请号：US12266201
申请日：2008-11-06
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Yong-Kyu Lee
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Yong-Kyu Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/785 , B82Y10/00 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L29/78645
摘要： According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.
摘要翻译：根据本发明的具有多栅极结构的非易失性存储器件及其形成方法，使用镶嵌工艺形成栅电极。因此，在用于形成栅电极的工艺中，电荷存储层，隧道绝缘层，阻挡绝缘层和栅极电极层不会被蚀刻侵蚀，从而形成具有良好可靠性的非易失性存储器件。

33. 发明授权

US07465985B2 Non-volatile memory device and methods of forming the same 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US07465985B2
公开(公告)日：2008-12-16
申请号：US11580086
申请日：2006-10-13
申请人： Byung-Yong Choi , Choong-Ho Lee , Dong-Gun Park
发明人： Byung-Yong Choi , Choong-Ho Lee , Dong-Gun Park
IPC分类号： H01L21/334
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.
摘要翻译：提供了一种非易失性存储器件及其形成方法。非易失性存储器件可以包括依次层叠在半导体衬底的预定或给定区域上的单元隔离图案和半导体图案，半导体图案上的单元栅极线和半导体衬底的一侧的顶表面上的半导体图案电池隔离图案，单元栅极线和半导体衬底之间的多层陷阱绝缘层，以及单元栅极线和半导体图案，在单元栅极线的两侧的半导体衬底中的第一杂质扩散层和位于单元栅极线两侧的半导体图案中的第二杂质扩散层。

34. 发明授权

US07402493B2 Method for forming non-volatile memory devices 有权
标题翻译：用于形成非易失性存储器件的方法
公开(公告)号：US07402493B2
公开(公告)日：2008-07-22
申请号：US11602032
申请日：2006-11-20
申请人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Yong-Kyu Lee
发明人： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Yong-Kyu Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , B82Y10/00 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L29/78645
摘要： According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.
摘要翻译：根据本发明的具有多栅极结构的非易失性存储器件及其形成方法，使用镶嵌工艺形成栅电极。因此，在用于形成栅电极的工艺中，电荷存储层，隧道绝缘层，阻挡绝缘层和栅极电极层不会被蚀刻侵蚀，从而形成具有良好可靠性的非易失性存储器件。

35. 发明授权

US07384850B2 Methods of forming complementary metal oxide semiconductor (CMOS) transistors having three-dimensional channel regions therein 有权
标题翻译：形成其中具有三维沟道区的互补金属氧化物半导体（CMOS）晶体管的方法
公开(公告)号：US07384850B2
公开(公告)日：2008-06-10
申请号：US11087988
申请日：2005-03-23
申请人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
发明人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
IPC分类号： H01L21/8234
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/66787 , H01L29/78645
摘要： An integrated circuit device containing complementary metal oxide semiconductor transistors includes a semiconductor substrate and an NMOS transistor having a first fin-shaped active region that extends in the semiconductor substrate. The first fin-shaped active region has a first channel region therein with a first height. A PMOS transistor is also provided. The PMOS transistor has a second fin-shaped active region that extends in the semiconductor substrate. This second fin-shaped active region has a second channel region therein with a second height unequal to the first height.
摘要翻译：包含互补金属氧化物半导体晶体管的集成电路器件包括半导体衬底和具有在半导体衬底中延伸的第一鳍状有源区的NMOS晶体管。第一鳍形有源区域在其中具有第一高度的第一通道区域。还提供PMOS晶体管。 PMOS晶体管具有在半导体衬底中延伸的第二鳍状有源区。该第二鳍形有源区域具有其中具有不等于第一高度的第二高度的第二沟道区域。

36. 发明授权

US07361956B2 Semiconductor device having partially insulated field effect transistor (PiFET) and method of fabricating the same 有权
标题翻译：具有部分绝缘的场效应晶体管（PiFET）的半导体器件及其制造方法
公开(公告)号：US07361956B2
公开(公告)日：2008-04-22
申请号：US10982554
申请日：2004-11-05
申请人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Min-Sang Kim , Sung-Min Kim
发明人： Chang-Woo Oh , Dong-Gun Park , Jeong-Dong Choe , Min-Sang Kim , Sung-Min Kim
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/823481 , H01L21/76283 , H01L29/1079 , H01L29/78
摘要： Embodiments of the invention include a partially insulated field effect transistor and a method of fabricating the same. According to some embodiments, a semiconductor substrate is formed by sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer. The sacrificial layer may be removed to form a buried gap region between the bottom semiconductor layer and the top semiconductor layer. Then, a transistor may be formed on the semiconductor substrate. The sacrificial layer may be a crystalline semiconductor formed by an epitaxial growth technology.
摘要翻译：本发明的实施例包括部分绝缘的场效应晶体管及其制造方法。根据一些实施例，通过顺序堆叠底部半导体层，牺牲层和顶部半导体层来形成半导体衬底。可以去除牺牲层以在底部半导体层和顶部半导体层之间形成掩埋间隙区域。然后，可以在半导体衬底上形成晶体管。牺牲层可以是通过外延生长技术形成的晶体半导体。

37. 发明授权

US07265031B2 Methods of fabricating semiconductor-on-insulator (SOI) substrates and semiconductor devices using sacrificial layers and void spaces 有权
标题翻译：使用牺牲层和空隙空间制造绝缘体上半导体（SOI）衬底和半导体器件的方法
公开(公告)号：US07265031B2
公开(公告)日：2007-09-04
申请号：US10972972
申请日：2004-10-25
申请人： Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe
发明人： Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/78603
摘要： An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.
摘要翻译：通过在其上提供具有牺牲层的衬底，在远离衬底的牺牲层上的有源半导体层和沿着有源半导体层和牺牲层的至少两侧延伸的支撑层来制造SOI衬底衬底，并且暴露出牺牲层的至少一侧。牺牲层中的至少一部分被蚀刻穿过其至少一侧，其被支撑层暴露以在衬底和有源半导体层之间形成空隙，使得有源半导体层以间隔的关系支撑通过支撑层从衬底。空隙空间可以至少部分地填充有绝缘体衬里。

38. 发明申请

US20060289907A1 Metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions and methods of fabricating the same 失效
标题翻译：具有低于源区和漏区的缓冲区的金属氧化物半导体（MOS）晶体管及其制造方法
公开(公告)号：US20060289907A1
公开(公告)日：2006-12-28
申请号：US11513474
申请日：2006-08-31
申请人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
发明人： Sung-Min Kim , Dong-Gun Park , Sung-Young Lee , Hye-Jin Cho , Eun-Jung Yun , Shin-Ae Lee , Chang-Woo Oh , Jeong-Dong Choe
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L29/66651 , H01L21/823412 , H01L21/823437 , H01L21/823487 , H01L29/0653
摘要： A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.
摘要翻译：在集成电路基板上设置有集成电路基板和MOS晶体管的金属氧化物半导体（MOS）晶体管的单位电池。 MOS晶体管具有源极区，漏极区和栅极。栅极在源极区域和漏极区域之间。第一和第二间隔开的缓冲区设置在源极区域和漏极区域之间以及源区域和集成电路衬底以及漏极区域和集成电路衬底中的相应区域之间。

39. 发明授权

US07084478B2 Load resistor with dummy contact substantially free of charge build up during etching process 有权
标题翻译：在蚀刻过程中负载电阻器具有基本上不含电荷的虚拟接触
公开(公告)号：US07084478B2
公开(公告)日：2006-08-01
申请号：US10270563
申请日：2002-10-16
申请人： Won Shik Lee , Joon-Mo Kwon , Tae Kyung Kim , Jin-Kee Choi , Dong-Gun Park , Hyeong-Chan Ko , Hong-Joon Moon
发明人： Won Shik Lee , Joon-Mo Kwon , Tae Kyung Kim , Jin-Kee Choi , Dong-Gun Park , Hyeong-Chan Ko , Hong-Joon Moon
IPC分类号： H01L29/00
CPC分类号： H01L28/20 , H01L27/0802
摘要： A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.
摘要翻译：制造具有负载电阻器的半导体器件，使得在负载电阻器的两端形成接触，并且在触点之间形成至少一个触点，以便防止在触点期间在每个触点内产生杂质通过蚀刻绝缘层产生的电荷产生，当蚀刻工艺制造绝缘层以在位于绝缘层下方的长负载电阻器中产生接触并在电和物理上绝缘时产生电荷现象。

40. 发明授权

US07056781B2 Method of forming fin field effect transistor 有权
标题翻译：形成鳍式场效应晶体管的方法
公开(公告)号：US07056781B2
公开(公告)日：2006-06-06
申请号：US11014212
申请日：2004-12-15
申请人： Jae-Man Yoon , Gyo-Young Jin , Hee-Soo Kang , Dong-Gun Park
发明人： Jae-Man Yoon , Gyo-Young Jin , Hee-Soo Kang , Dong-Gun Park
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7854 , H01L29/78609
摘要： According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.
摘要翻译：根据一些实施例，在半导体衬底上的侧壁的曝光状态下形成鳍型有源区。在有源区的上部和侧壁上形成栅极绝缘层，并且器件隔离膜将活性区域包围到有源区的上部高度。侧壁由形成在器件隔离膜上的开口部分部分露出。开口部分填充有部分覆盖有源区的上部的导电层，形成栅电极。源极和漏极区域在栅电极不是的有源区域的一部分上。可以容易地分离栅极电极，并且可以显着地减少由蚀刻副产物引起的问题，并且可以防止沟道区域的漏电流和电场集中在边缘部分上。

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