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31. 发明授权

US09214402B2 Pressure sensor device with gel retainer 有权
标题翻译：带有凝胶保持器的压力传感器装置
公开(公告)号：US09214402B2
公开(公告)日：2015-12-15
申请号：US14151811
申请日：2014-01-10
申请人： Kee Cheong Fam , Mohd Rusli Ibrahim , Lan Chu Tan
发明人： Kee Cheong Fam , Mohd Rusli Ibrahim , Lan Chu Tan
IPC分类号： H01L23/24 , H01L23/00 , H01L21/56 , H01L29/84 , H01L23/31
CPC分类号： H01L24/83 , H01L21/56 , H01L23/24 , H01L23/3121 , H01L23/3135 , H01L24/29 , H01L24/45 , H01L29/84 , H01L2224/2919 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/48137 , H01L2224/73265 , H01L2224/83101 , H01L2224/92247 , H01L2924/11 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2924/0665
摘要： A pressure sensor device includes a gel retainer that is mounted or formed on a substrate. The gel retainer has a cavity and a pressure sensing die is mounted inside the cavity. The die is electrically connected to one or more other package elements. A pressure-sensitive gel material is dispensed into the cavity to cover an active region of the pressure sensing die. A mold compound is applied on an upper surface of the substrate outside of the gel retainer.
摘要翻译：压力传感器装置包括安装或形成在基底上的凝胶保持器。凝胶保持器具有空腔，并且压力感测模具安装在腔体内。模具电连接到一个或多个其它封装元件。将压敏凝胶材料分配到空腔中以覆盖压力感测模具的有源区域。将模具化合物施加在凝胶保持器外部的基板的上表面上。

32. 发明授权

US09177834B2 Power bar design for lead frame-based packages 有权
标题翻译：电源棒设计用于引线框架封装
公开(公告)号：US09177834B2
公开(公告)日：2015-11-03
申请号：US14184672
申请日：2014-02-19
申请人： Chee Seng Foong , Meng Kong Lye , Lan Chu Tan , Seng Kiong Teng
发明人： Chee Seng Foong , Meng Kong Lye , Lan Chu Tan , Seng Kiong Teng
IPC分类号： H01L23/495 , H01L21/56 , H01L23/31 , H01L23/00
CPC分类号： H01L21/56 , H01L23/3107 , H01L23/49541 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/72 , H01L24/73 , H01L24/85 , H01L2224/27334 , H01L2224/2919 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45664 , H01L2224/48245 , H01L2224/732 , H01L2224/73265 , H01L2224/85 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2924/00014 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/0665 , H01L2224/48 , H01L2224/72
摘要： A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.
摘要翻译：半导体器件包括封装在封装壳体中并具有四个主侧壁的半导体管芯，每个主侧壁大致平行于第一或第二正交方向之一。信号引线电耦合到管芯，并且每个具有从主侧壁中的一个平行于第一或第二方向之一延伸的暴露部分。一个或多个电源杆电耦合到管芯，并且每个具有至少一个相对于第一和第二方向以非零角度延伸的电源杆引线。电源条和相关的电源条引线与信号引线电隔离。一个或多个连接杆相对于第一和第二方向以大致非零的角度延伸，并且与信号引线和功率条以及相关联的功率条引线电隔离。

33. 发明申请

US20150235924A1 POWER BAR DESIGN FOR LEAD FRAME-BASED PACKAGES 有权
标题翻译：用于基于框架的包装的电源条设计
公开(公告)号：US20150235924A1
公开(公告)日：2015-08-20
申请号：US14184672
申请日：2014-02-19
申请人： Chee Seng Foong , Meng Kong Lye , Lan Chu Tan , Seng Kiong Teng
发明人： Chee Seng Foong , Meng Kong Lye , Lan Chu Tan , Seng Kiong Teng
IPC分类号： H01L23/495 , H01L23/00 , H01L21/56 , H01L23/31
CPC分类号： H01L21/56 , H01L23/3107 , H01L23/49541 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/72 , H01L24/73 , H01L24/85 , H01L2224/27334 , H01L2224/2919 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45664 , H01L2224/48245 , H01L2224/732 , H01L2224/73265 , H01L2224/85 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2924/00014 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/0665 , H01L2224/48 , H01L2224/72
摘要： A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.
摘要翻译：半导体器件包括封装在封装壳体中并具有四个主侧壁的半导体管芯，每个主侧壁大致平行于第一或第二正交方向之一。信号引线电耦合到管芯，并且每个具有从主侧壁中的一个平行于第一或第二方向之一延伸的暴露部分。一个或多个电源杆电耦合到管芯，并且每个具有至少一个相对于第一和第二方向以非零角度延伸的电源杆引线。电源条和相关的电源条引线与信号引线电隔离。一个或多个连接杆相对于第一和第二方向以大致非零的角度延伸，并且与信号引线和功率条以及相关联的功率条引线电隔离。

34. 发明申请

US20150187728A1 EMICONDUCTOR DEVICE WITH DIE TOP POWER CONNECTIONS 审中-公开
标题翻译：具有DIE顶部电源连接的EMICONDUCTOR DEVICE
公开(公告)号：US20150187728A1
公开(公告)日：2015-07-02
申请号：US14141465
申请日：2013-12-27
申请人： Kesvakumar V.C. Muniandy , Navas Khan Oratti Kalandar , Lan Chu Tan
发明人： Kesvakumar V.C. Muniandy , Navas Khan Oratti Kalandar , Lan Chu Tan
IPC分类号： H01L23/00
CPC分类号： H01L24/03 , H01L23/5286 , H01L23/5328 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/05553 , H01L2224/06135 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/14 , H01L2924/00012 , H01L2224/45099 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207
摘要： In a packaged semiconductor device, a die is mounted on a substrate having power connection pads. An exterior (e.g., top) surface of the die has power bond pads and distributed power feed pads. Bond wires electrically connect the power connection pads of the substrate to the power bond pads of the die, and exterior conductive structures electrically connect the power bond pads of the die to the distributed power feed pads of the die. The exterior conductive structures are printed or pasted onto the exterior die surface. Using exterior conductive structures instead of interior conductive traces (in the die) reduces resistive power losses and frees up more room for routing signals within the interior die layers.
摘要翻译：在封装半导体器件中，裸片安装在具有电源连接焊盘的基板上。管芯的外部（例如顶部）表面具有电力接合焊盘和分布式馈电焊盘。接合线将衬底的电源连接焊盘电连接到管芯的电源接合焊盘，并且外部导电结构将管芯的功率接合焊盘电连接到管芯的分布式馈电焊盘。外部导电结构被印刷或粘贴到外部模具表面上。使用外部导电结构代替内部导电迹线（在管芯中）可以降低电阻功率损耗，并释放更多的内部管芯层内路由信号的空间。

35. 发明申请

US20150097278A1 SURFACE MOUNT SEMICONDUCTOR DEVICE WITH ADDITIONAL BOTTOM FACE CONTACTS 审中-公开
标题翻译：表面安装半导体器件与附加底部表面接触
公开(公告)号：US20150097278A1
公开(公告)日：2015-04-09
申请号：US14459328
申请日：2014-08-14
申请人： Zhigang Bai , Yin Kheng Au , Lan Chu Tan , Jinzhong Yao
发明人： Zhigang Bai , Yin Kheng Au , Lan Chu Tan , Jinzhong Yao
IPC分类号： H01L23/495
CPC分类号： H01L21/4842 , H01L23/49541 , H01L23/49551 , H01L23/49558 , H01L24/73 , H01L2224/04042 , H01L2224/05554 , H01L2224/06135 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/73265 , H01L2924/181 , H01L2924/00012
摘要： Assembling a surface mount semiconductor device includes providing a lead frame structure with peripheral leads and additional bottom face contacts integral with frame members. Outer portions of the bottom face contact members are interposed between inner portions of adjacent pairs of the peripheral leads. A package body is formed by encapsulating the lead frame structure in which the frame members are positioned outside a side edge surface. The peripheral leads and the bottom face contact members project between the side edge surface of the package body and the frame members. The frame members are cut and the peripheral leads and the bottom face contact members are separated and electrically isolated from each other.
摘要翻译：组装表面贴装半导体器件包括提供具有周边引线的引线框结构和与框架构件一体的附加底面接触。底面接触构件的外部部分位于相邻的外围引线对的内部之间。通过封装框架构件定位在侧边缘表面外侧的引线框架结构形成封装体。外围引线和底面接触构件在封装主体的侧边缘表面和框架构件之间突出。框架构件被切割，并且周边引线和底面接触构件彼此分离并电隔离。

36. 发明授权

US08669140B1 Method of forming stacked die package using redistributed chip packaging 有权
标题翻译：使用重新分配的芯片封装形成堆叠芯片封装的方法
公开(公告)号：US08669140B1
公开(公告)日：2014-03-11
申请号：US13857143
申请日：2013-04-04
申请人： Kesvakumar V. C. Muniandy , Navas Khan Oratti Kalandar , Lan Chu Tan
发明人： Kesvakumar V. C. Muniandy , Navas Khan Oratti Kalandar , Lan Chu Tan
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44
CPC分类号： H01L24/20 , H01L21/568 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/19 , H01L2224/221 , H01L2224/2518 , H01L2224/2919 , H01L2224/32135 , H01L2224/32145 , H01L2224/45144 , H01L2224/48228 , H01L2224/73253 , H01L2224/73265 , H01L2224/81005 , H01L2224/81192 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/014 , H01L2224/48227 , H01L2924/00012 , H01L2924/00 , H01L2224/83005
摘要： A method of making a semiconductor device includes providing a first semiconductor die and a conductive frame member having at least one conductive via. A first encapsulation layer is formed. A first redistribution layer is formed opposite the first encapsulation layer. A second redistribution layer is formed opposite the first redistribution layer. A second semiconductor die is mounted and electrically connected with receptor pads in the second redistribution layer. A third semiconductor die is mounted to the second semiconductor die and electrically connected with bond wires to a conductor in the second redistribution layer. A second encapsulation layer embeds the second and third semiconductor dies, the wires, and the conductor in the second redistribution layer.
摘要翻译：制造半导体器件的方法包括提供具有至少一个导电通孔的第一半导体管芯和导电框架构件。形成第一封装层。第一再分配层与第一封装层相对地形成。形成与第一再分配层相对的第二再分配层。第二半导体管芯安装并与第二再分配层中的接收器焊盘电连接。第三半导体管芯安装到第二半导体管芯并且与接合线电连接到第二再分配层中的导体。第二封装层将第二和第三半导体管芯，导线和导体嵌入第二再分布层。

37. 发明申请

US20120073859A1 POLYMER CORE WIRE 审中-公开
标题翻译：聚合物芯线
公开(公告)号：US20120073859A1
公开(公告)日：2012-03-29
申请号：US12889428
申请日：2010-09-24
申请人： Wai Yew Lo , Yit Meng Lee , Lan Chu Tan
发明人： Wai Yew Lo , Yit Meng Lee , Lan Chu Tan
IPC分类号： H01B5/14 , B05D5/12 , H01B13/00 , C25D5/54
CPC分类号： H01L24/745 , H01L24/43 , H01L24/45 , H01L2224/43 , H01L2224/45015 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/45164 , H01L2224/4519 , H01L2224/45193 , H01L2224/45565 , H01L2224/45572 , H01L2224/456 , H01L2224/45624 , H01L2224/45644 , H01L2224/45647 , H01L2224/45655 , H01L2224/45664 , H01L2224/745 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/48 , H01L2924/20759 , H01L2924/2076 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/00015 , H01L2924/2075 , H01L2924/20754
摘要： A wire capable of conducting electrical current has a polymer core and a coating layer surrounding the core. The coating layer, which may be, for example, gold or copper, conducts electrical current and the core provides strength so that the wire is able to withstand bending and breakage. Among other things, the polymer core wire is useful for connecting an integrated circuit to a lead frame or substrate.
摘要翻译：能够导电的线具有聚合物芯和围绕芯的涂层。可以是例如金或铜的涂层传导电流，并且芯提供强度，使得电线能够承受弯曲和断裂。其中，聚合物芯线可用于将集成电路连接到引线框架或基板。

38. 发明申请

US20110059579A1 METHOD OF FORMING TAPE BALL GRID ARRAY PACKAGE 审中-公开
标题翻译：形成磁带阵列阵列封装的方法
公开(公告)号：US20110059579A1
公开(公告)日：2011-03-10
申请号：US12554992
申请日：2009-09-08
申请人： Poh Leng Eu , Lan Chu Tan , Cheng Qiang Cui
发明人： Poh Leng Eu , Lan Chu Tan , Cheng Qiang Cui
IPC分类号： H01L21/50
CPC分类号： H01L21/6835 , H01L21/568 , H01L23/4985 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2221/68345 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83907 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/18165 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A method of forming a semiconductor package including providing a substrate having a through hole formed therein. A tape is attached to a surface of the substrate such that the through hole is covered by the tape. An integrated circuit (IC) die is attached to the tape. The IC die is electrically connected to the substrate via a plurality of electrical connections. The IC die and the electrical connections are encapsulated and the tape is removed from the substrate.
摘要翻译：一种形成半导体封装的方法，包括提供其中形成有通孔的衬底。胶带附着在基材的表面上，使得通孔被带覆盖。集成电路（IC）裸片连接在磁带上。 IC芯片通过多个电连接与基板电连接。封装IC芯片和电气连接，并从基板上取下胶带。

39. 发明授权

US07741196B2 Semiconductor wafer with improved crack protection 有权
标题翻译：半导体晶圆具有改进的裂纹保护
公开(公告)号：US07741196B2
公开(公告)日：2010-06-22
申请号：US11668453
申请日：2007-01-29
申请人： Heng Keong Yip , Wai Yew Lo , Lan Chu Tan
发明人： Heng Keong Yip , Wai Yew Lo , Lan Chu Tan
IPC分类号： H01L21/30
CPC分类号： H01L21/3043 , H01L21/02118 , H01L21/312 , H01L21/78 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool. Within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.
摘要翻译：制造用于切割的半导体晶片的方法包括在基板上提供包括基板和多个上层的半导体晶片，形成管芯区域的形成。该结构布置成使得相邻的模具区域被用于切割工具的路径分开。在每个路径中，制造一对间隔开的线。每条线限定相应路径的切割边缘，并且具有在晶片的顶表面和基底之间延伸的至少一个沟槽。每个沟槽填充有应力吸收材料，用于在切割期间减少模具区域上的模具工具引起的应力。

40. 发明授权

US06900531B2 Image sensor device 有权
标题翻译：图像传感器装置
公开(公告)号：US06900531B2
公开(公告)日：2005-05-31
申请号：US10280952
申请日：2002-10-25
申请人： Chee Seng Foong , Kok Wai Mui , Kim Heng Tan , Lan Chu Tan
发明人： Chee Seng Foong , Kok Wai Mui , Kim Heng Tan , Lan Chu Tan
IPC分类号： H01L23/10 , H01L23/22 , H01L27/14 , H01L27/146 , H01L31/0203 , H04N5/369
CPC分类号： H01L27/14634 , H01L27/14618 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2924/15311 , H01L2924/16195 , H01L2924/00014
摘要： An image sensor device is made using an ultra-thin substrate so that the overall device height is less than 1.0 mm. The image sensor includes a flexible circuit substrate having first and second opposing sides, the first side having a central area and an outer, bonding pad area including bonding pads. A sensor integrated circuit (IC) is attached to the central area of the first side of the circuit substrate. The IC has an active area and a peripheral bonding pad area including bonding pads. Wires are wirebonded to respective ones of the IC bonding pads and corresponding ones of the circuit substrate bonding pads to electrically connect the IC and the circuit substrate. A wall having a first end with a step and a second end has its second end attached to an outer portion beyond the outer bonding pad area of the first side of the flexible circuit substrate. The wall at least partially surrounds the sensor integrated circuit. A transparent cover is located above the IC such that light can pass through the cover onto the IC active area. Opposing edges of the cover are secured within the step of the wall. Solder balls are attached to the second side of the circuit substrate. The circuit substrate provides for electrical interconnect between the solder balls and the bonding pads on the first side of the circuit substrate.
摘要翻译：使用超薄基板制造图像传感器装置，使得整个装置高度小于1.0mm。图像传感器包括具有第一和第二相对侧的柔性电路基板，第一侧具有包括接合焊盘的中心区域和外部焊接区域。传感器集成电路（IC）附接到电路基板的第一侧的中心区域。 IC具有包括接合焊盘的有源区和外围接合焊盘区域。电线与各个IC接合焊盘和对应的电路衬底接合焊盘引线接合，以电连接IC和电路衬底。具有台阶和第二端的第一端的壁的第二端具有附接到柔性电路基板的第一侧的外部焊盘区域外部的外部部分。墙壁至少部分地围绕传感器集成电路。透明盖位于IC上方，使得光可以穿过盖到IC活动区域。盖的相对边缘固定在墙壁的台阶内。焊球附接到电路基板的第二侧。电路基板提供焊球和电路基板第一面上的接合焊盘之间的电互连。

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